x86: move more x86-generic functions out of PC files
These are needed by microvm too, so move them outside of PC-specific files. With this patch, microvm.c need not include pc.h anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
4ca8dabdb8
commit
89a289c7e9
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@ -53,6 +53,7 @@
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/* Supported chipsets: */
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/* Supported chipsets: */
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#include "hw/southbridge/piix.h"
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#include "hw/southbridge/piix.h"
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#include "hw/acpi/pcihp.h"
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#include "hw/acpi/pcihp.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/i386/ich9.h"
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#include "hw/i386/ich9.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-host/q35.h"
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#include "hw/pci-host/q35.h"
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@ -16,7 +16,6 @@
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#include "sysemu/numa.h"
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#include "sysemu/numa.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/acpi.h"
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#include "hw/firmware/smbios.h"
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#include "hw/firmware/smbios.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/timer/hpet.h"
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#include "hw/timer/hpet.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/nvram/fw_cfg.h"
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@ -12,6 +12,8 @@
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#include "hw/boards.h"
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#include "hw/boards.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/nvram/fw_cfg.h"
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#define FW_CFG_IO_BASE 0x510
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
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@ -12,7 +12,7 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "monitor/monitor.h"
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#include "monitor/monitor.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/x86.h"
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#include "hw/irq.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties.h"
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#include "hw/i386/ioapic_internal.h"
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#include "hw/i386/ioapic_internal.h"
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@ -32,7 +32,6 @@
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#include "hw/kvm/clock.h"
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#include "hw/kvm/clock.h"
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#include "hw/i386/microvm.h"
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#include "hw/i386/microvm.h"
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#include "hw/i386/x86.h"
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#include "hw/i386/x86.h"
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#include "hw/i386/pc.h"
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#include "target/i386/cpu.h"
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#include "target/i386/cpu.h"
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#include "hw/intc/i8259.h"
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#include "hw/intc/i8259.h"
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#include "hw/timer/i8254.h"
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#include "hw/timer/i8254.h"
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@ -133,7 +132,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
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if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
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if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
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qemu_irq *i8259;
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qemu_irq *i8259;
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i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
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i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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gsi_state->i8259_irq[i] = i8259[i];
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gsi_state->i8259_irq[i] = i8259[i];
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}
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}
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101
hw/i386/pc.c
101
hw/i386/pc.c
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@ -337,17 +337,6 @@ GlobalProperty pc_compat_1_4[] = {
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};
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};
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const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
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const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
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void gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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trace_pc_gsi_interrupt(n, level);
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if (n < ISA_NUM_IRQS) {
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qemu_set_irq(s->i8259_irq[n], level);
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}
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
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GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
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{
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{
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GSIState *s;
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GSIState *s;
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@ -387,55 +376,6 @@ static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
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return 0xffffffffffffffffULL;
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return 0xffffffffffffffffULL;
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}
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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return cpu_get_ticks();
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUX86State *env)
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{
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X86CPU *cpu = env_archcpu(env);
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int intno;
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if (!kvm_irqchip_in_kernel()) {
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intno = apic_get_interrupt(cpu->apic_state);
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if (intno >= 0) {
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return intno;
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}
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(cpu->apic_state)) {
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return -1;
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}
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}
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intno = pic_read_irq(isa_pic);
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return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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CPUState *cs = first_cpu;
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X86CPU *cpu = X86_CPU(cs);
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trace_pc_pic_interrupt(irq, level);
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if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
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CPU_FOREACH(cs) {
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cpu = X86_CPU(cs);
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if (apic_accept_pic_intr(cpu->apic_state)) {
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apic_deliver_pic_intr(cpu->apic_state, level);
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}
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}
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} else {
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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/* PC cmos mappings */
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14
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#define REG_EQUIPMENT_BYTE 0x14
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@ -879,16 +819,6 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
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nb_ne2k++;
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nb_ne2k++;
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}
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}
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DeviceState *cpu_get_current_apic(void)
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{
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if (current_cpu) {
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X86CPU *cpu = X86_CPU(current_cpu);
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return cpu->apic_state;
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} else {
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return NULL;
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}
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}
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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{
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{
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X86CPU *cpu = opaque;
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X86CPU *cpu = opaque;
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@ -1284,11 +1214,6 @@ uint64_t pc_pci_hole64_start(void)
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return ROUND_UP(hole64_start, 1 * GiB);
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return ROUND_UP(hole64_start, 1 * GiB);
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}
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}
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qemu_irq pc_allocate_cpu_irq(void)
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{
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return qemu_allocate_irq(pic_irq_request, NULL, 0);
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}
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DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
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DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
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{
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{
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DeviceState *dev = NULL;
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DeviceState *dev = NULL;
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@ -1465,7 +1390,7 @@ void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
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} else if (xen_enabled()) {
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} else if (xen_enabled()) {
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i8259 = xen_interrupt_controller_init();
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i8259 = xen_interrupt_controller_init();
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} else {
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} else {
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i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
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i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
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}
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}
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for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
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for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
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@ -1475,30 +1400,6 @@ void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
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g_free(i8259);
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g_free(i8259);
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}
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}
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void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
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{
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DeviceState *dev;
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SysBusDevice *d;
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unsigned int i;
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if (kvm_ioapic_in_kernel()) {
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dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
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} else {
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dev = qdev_create(NULL, TYPE_IOAPIC);
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}
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if (parent_name) {
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object_property_add_child(object_resolve_path(parent_name, NULL),
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"ioapic", OBJECT(dev), NULL);
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}
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qdev_init_nofail(dev);
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d = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
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}
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}
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static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
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static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp)
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Error **errp)
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{
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{
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@ -112,8 +112,10 @@ amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64
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vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"
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vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"
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vmport_command(unsigned char command) "command: 0x%02x"
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vmport_command(unsigned char command) "command: 0x%02x"
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# x86.c
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x86_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d"
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x86_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d"
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# pc.c
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# pc.c
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pc_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d"
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pc_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d"
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port92_read(uint8_t val) "port92: read 0x%02x"
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port92_read(uint8_t val) "port92: read 0x%02x"
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port92_write(uint8_t val) "port92: write 0x%02x"
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port92_write(uint8_t val) "port92: write 0x%02x"
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103
hw/i386/x86.c
103
hw/i386/x86.c
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@ -34,6 +34,7 @@
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#include "sysemu/numa.h"
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#include "sysemu/numa.h"
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#include "sysemu/replay.h"
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#include "sysemu/replay.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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#include "hw/i386/x86.h"
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#include "hw/i386/x86.h"
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#include "target/i386/cpu.h"
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#include "target/i386/cpu.h"
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#include "hw/intc/i8259.h"
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#include "hw/intc/i8259.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/irq.h"
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#include "hw/nmi.h"
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#include "hw/nmi.h"
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#include "hw/loader.h"
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#include "hw/loader.h"
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#include "multiboot.h"
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#include "multiboot.h"
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#include "elf.h"
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#include "elf.h"
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#include "standard-headers/asm-x86/bootparam.h"
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#include "standard-headers/asm-x86/bootparam.h"
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#include "config-devices.h"
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#include "kvm_i386.h"
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#define BIOS_FILENAME "bios.bin"
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#define BIOS_FILENAME "bios.bin"
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return size;
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return size;
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}
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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return cpu_get_ticks();
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}
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/* IRQ handling */
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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CPUState *cs = first_cpu;
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X86CPU *cpu = X86_CPU(cs);
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trace_x86_pic_interrupt(irq, level);
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if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
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CPU_FOREACH(cs) {
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cpu = X86_CPU(cs);
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if (apic_accept_pic_intr(cpu->apic_state)) {
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apic_deliver_pic_intr(cpu->apic_state, level);
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}
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}
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} else {
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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qemu_irq x86_allocate_cpu_irq(void)
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{
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return qemu_allocate_irq(pic_irq_request, NULL, 0);
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}
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int cpu_get_pic_interrupt(CPUX86State *env)
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{
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X86CPU *cpu = env_archcpu(env);
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int intno;
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if (!kvm_irqchip_in_kernel()) {
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intno = apic_get_interrupt(cpu->apic_state);
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if (intno >= 0) {
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return intno;
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}
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(cpu->apic_state)) {
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return -1;
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}
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}
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intno = pic_read_irq(isa_pic);
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return intno;
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}
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DeviceState *cpu_get_current_apic(void)
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{
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if (current_cpu) {
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X86CPU *cpu = X86_CPU(current_cpu);
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return cpu->apic_state;
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} else {
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return NULL;
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}
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}
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void gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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trace_x86_gsi_interrupt(n, level);
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if (n < ISA_NUM_IRQS) {
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qemu_set_irq(s->i8259_irq[n], level);
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}
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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|
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||||||
|
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
|
||||||
|
{
|
||||||
|
DeviceState *dev;
|
||||||
|
SysBusDevice *d;
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
if (kvm_ioapic_in_kernel()) {
|
||||||
|
dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
|
||||||
|
} else {
|
||||||
|
dev = qdev_create(NULL, TYPE_IOAPIC);
|
||||||
|
}
|
||||||
|
if (parent_name) {
|
||||||
|
object_property_add_child(object_resolve_path(parent_name, NULL),
|
||||||
|
"ioapic", OBJECT(dev), NULL);
|
||||||
|
}
|
||||||
|
qdev_init_nofail(dev);
|
||||||
|
d = SYS_BUS_DEVICE(dev);
|
||||||
|
sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
|
||||||
|
|
||||||
|
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
||||||
|
gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
struct setup_data {
|
struct setup_data {
|
||||||
uint64_t next;
|
uint64_t next;
|
||||||
uint32_t type;
|
uint32_t type;
|
||||||
|
|
|
@ -3,11 +3,9 @@
|
||||||
|
|
||||||
#include "exec/memory.h"
|
#include "exec/memory.h"
|
||||||
#include "hw/boards.h"
|
#include "hw/boards.h"
|
||||||
#include "hw/isa/isa.h"
|
|
||||||
#include "hw/block/fdc.h"
|
#include "hw/block/fdc.h"
|
||||||
#include "hw/block/flash.h"
|
#include "hw/block/flash.h"
|
||||||
#include "net/net.h"
|
#include "net/net.h"
|
||||||
#include "hw/i386/ioapic.h"
|
|
||||||
#include "hw/i386/x86.h"
|
#include "hw/i386/x86.h"
|
||||||
|
|
||||||
#include "qemu/range.h"
|
#include "qemu/range.h"
|
||||||
|
@ -134,17 +132,6 @@ typedef struct PCMachineClass {
|
||||||
|
|
||||||
/* ioapic.c */
|
/* ioapic.c */
|
||||||
|
|
||||||
/* Global System Interrupts */
|
|
||||||
|
|
||||||
#define GSI_NUM_PINS IOAPIC_NUM_PINS
|
|
||||||
|
|
||||||
typedef struct GSIState {
|
|
||||||
qemu_irq i8259_irq[ISA_NUM_IRQS];
|
|
||||||
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
|
|
||||||
} GSIState;
|
|
||||||
|
|
||||||
void gsi_handler(void *opaque, int n, int level);
|
|
||||||
|
|
||||||
GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
|
GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
|
||||||
|
|
||||||
/* vmport.c */
|
/* vmport.c */
|
||||||
|
@ -188,7 +175,6 @@ void pc_memory_init(PCMachineState *pcms,
|
||||||
MemoryRegion *rom_memory,
|
MemoryRegion *rom_memory,
|
||||||
MemoryRegion **ram_memory);
|
MemoryRegion **ram_memory);
|
||||||
uint64_t pc_pci_hole64_start(void);
|
uint64_t pc_pci_hole64_start(void);
|
||||||
qemu_irq pc_allocate_cpu_irq(void);
|
|
||||||
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
|
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
|
||||||
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
|
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
|
||||||
ISADevice **rtc_state,
|
ISADevice **rtc_state,
|
||||||
|
@ -206,18 +192,12 @@ void pc_pci_device_init(PCIBus *pci_bus);
|
||||||
typedef void (*cpu_set_smm_t)(int smm, void *arg);
|
typedef void (*cpu_set_smm_t)(int smm, void *arg);
|
||||||
|
|
||||||
void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
|
void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
|
||||||
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
|
|
||||||
|
|
||||||
ISADevice *pc_find_fdc0(void);
|
ISADevice *pc_find_fdc0(void);
|
||||||
int cmos_get_fd_drive_type(FloppyDriveType fd0);
|
int cmos_get_fd_drive_type(FloppyDriveType fd0);
|
||||||
|
|
||||||
#define FW_CFG_IO_BASE 0x510
|
|
||||||
|
|
||||||
#define PORT92_A20_LINE "a20"
|
#define PORT92_A20_LINE "a20"
|
||||||
|
|
||||||
/* hpet.c */
|
|
||||||
extern int no_hpet;
|
|
||||||
|
|
||||||
/* pc_sysfw.c */
|
/* pc_sysfw.c */
|
||||||
void pc_system_flash_create(PCMachineState *pcms);
|
void pc_system_flash_create(PCMachineState *pcms);
|
||||||
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
|
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
|
||||||
|
|
|
@ -23,6 +23,8 @@
|
||||||
|
|
||||||
#include "hw/boards.h"
|
#include "hw/boards.h"
|
||||||
#include "hw/nmi.h"
|
#include "hw/nmi.h"
|
||||||
|
#include "hw/isa/isa.h"
|
||||||
|
#include "hw/i386/ioapic.h"
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
/*< private >*/
|
/*< private >*/
|
||||||
|
@ -100,4 +102,20 @@ void x86_load_linux(X86MachineState *x86ms,
|
||||||
|
|
||||||
bool x86_machine_is_smm_enabled(X86MachineState *x86ms);
|
bool x86_machine_is_smm_enabled(X86MachineState *x86ms);
|
||||||
|
|
||||||
|
/* Global System Interrupts */
|
||||||
|
|
||||||
|
#define GSI_NUM_PINS IOAPIC_NUM_PINS
|
||||||
|
|
||||||
|
typedef struct GSIState {
|
||||||
|
qemu_irq i8259_irq[ISA_NUM_IRQS];
|
||||||
|
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
|
||||||
|
} GSIState;
|
||||||
|
|
||||||
|
qemu_irq x86_allocate_cpu_irq(void);
|
||||||
|
void gsi_handler(void *opaque, int n, int level);
|
||||||
|
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
|
||||||
|
|
||||||
|
/* hpet.c */
|
||||||
|
extern int no_hpet;
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -35,7 +35,7 @@
|
||||||
#include "qemu/main-loop.h"
|
#include "qemu/main-loop.h"
|
||||||
#include "qemu/config-file.h"
|
#include "qemu/config-file.h"
|
||||||
#include "qemu/error-report.h"
|
#include "qemu/error-report.h"
|
||||||
#include "hw/i386/pc.h"
|
#include "hw/i386/x86.h"
|
||||||
#include "hw/i386/apic.h"
|
#include "hw/i386/apic.h"
|
||||||
#include "hw/i386/apic_internal.h"
|
#include "hw/i386/apic_internal.h"
|
||||||
#include "hw/i386/apic-msidef.h"
|
#include "hw/i386/apic-msidef.h"
|
||||||
|
|
|
@ -1,10 +1,10 @@
|
||||||
#include "qemu/osdep.h"
|
#include "qemu/osdep.h"
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "exec/exec-all.h"
|
#include "exec/exec-all.h"
|
||||||
#include "hw/i386/pc.h"
|
|
||||||
#include "hw/isa/isa.h"
|
#include "hw/isa/isa.h"
|
||||||
#include "migration/cpu.h"
|
#include "migration/cpu.h"
|
||||||
#include "hyperv.h"
|
#include "hyperv.h"
|
||||||
|
#include "hw/i386/x86.h"
|
||||||
#include "kvm_i386.h"
|
#include "kvm_i386.h"
|
||||||
|
|
||||||
#include "sysemu/kvm.h"
|
#include "sysemu/kvm.h"
|
||||||
|
|
Loading…
Reference in a new issue