target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order
When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
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static inline int fpr_offset(int i)
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static inline int fpr_offset(int i)
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{
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{
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return offsetof(CPUPPCState, vsr[i].u64[0]);
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return offsetof(CPUPPCState, vsr[i].VsrD(0));
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}
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}
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static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
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static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
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@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
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static inline int vsrl_offset(int i)
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static inline int vsrl_offset(int i)
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{
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{
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return offsetof(CPUPPCState, vsr[i].u64[1]);
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return offsetof(CPUPPCState, vsr[i].VsrD(1));
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}
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}
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static inline int vsr_full_offset(int i)
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static inline int vsr_full_offset(int i)
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@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
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static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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{
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{
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vsr->VsrD(0) = env->vsr[n].u64[0];
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vsr->VsrD(0) = env->vsr[n].VsrD(0);
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vsr->VsrD(1) = env->vsr[n].u64[1];
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vsr->VsrD(1) = env->vsr[n].VsrD(1);
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}
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}
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static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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{
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{
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env->vsr[n].u64[0] = vsr->VsrD(0);
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env->vsr[n].VsrD(0) = vsr->VsrD(0);
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env->vsr[n].u64[1] = vsr->VsrD(1);
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env->vsr[n].VsrD(1) = vsr->VsrD(1);
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}
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}
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void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
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void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
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@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size,
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{
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{
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ppc_vsr_t *v = pv;
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ppc_vsr_t *v = pv;
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v->u64[0] = qemu_get_be64(f);
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v->VsrD(0) = qemu_get_be64(f);
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return 0;
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return 0;
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}
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}
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@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size,
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{
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{
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ppc_vsr_t *v = pv;
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ppc_vsr_t *v = pv;
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qemu_put_be64(f, v->u64[0]);
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qemu_put_be64(f, v->VsrD(0));
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return 0;
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return 0;
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}
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}
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@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size,
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{
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{
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ppc_vsr_t *v = pv;
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ppc_vsr_t *v = pv;
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v->u64[1] = qemu_get_be64(f);
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v->VsrD(1) = qemu_get_be64(f);
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return 0;
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return 0;
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}
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}
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@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size,
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{
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{
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ppc_vsr_t *v = pv;
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ppc_vsr_t *v = pv;
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qemu_put_be64(f, v->u64[1]);
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qemu_put_be64(f, v->VsrD(1));
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return 0;
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return 0;
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}
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}
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