support for opaque data on memory I/Os - PCI ROM memory support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@876 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
8998028497
commit
8a8696a3c4
121
hw/pci.c
121
hw/pci.c
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@ -100,7 +100,7 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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{
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PCIIORegion *r;
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if ((unsigned int)region_num >= 6)
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if ((unsigned int)region_num >= PCI_NUM_REGIONS)
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return;
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r = &pci_dev->io_regions[region_num];
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r->addr = -1;
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@ -125,16 +125,21 @@ static void pci_update_mappings(PCIDevice *d)
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{
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PCIIORegion *r;
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int cmd, i;
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uint32_t last_addr, new_addr;
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uint32_t last_addr, new_addr, config_ofs;
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
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for(i = 0; i < 6; i++) {
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4;
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}
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if (r->size != 0) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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config_ofs));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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@ -148,7 +153,10 @@ static void pci_update_mappings(PCIDevice *d)
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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0x10 + i * 4));
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config_ofs));
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & 1))
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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@ -160,6 +168,7 @@ static void pci_update_mappings(PCIDevice *d)
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new_addr = -1;
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}
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} else {
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no_mem_map:
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new_addr = -1;
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}
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}
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@ -216,18 +225,28 @@ void pci_default_write_config(PCIDevice *d,
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int can_write, i;
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uint32_t end, addr;
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if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
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if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
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(address >= 0x30 && address < 0x34))) {
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PCIIORegion *r;
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int reg;
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reg = (address - 0x10) >> 2;
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if ( address >= 0x30 ) {
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reg = PCI_ROM_SLOT;
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}else{
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reg = (address - 0x10) >> 2;
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}
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r = &d->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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/* compute the stored value */
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val &= ~(r->size - 1);
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val |= r->type;
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*(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
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if (reg == PCI_ROM_SLOT) {
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/* keep ROM enable bit */
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val &= (~(r->size - 1)) | 1;
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} else {
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val &= ~(r->size - 1);
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val |= r->type;
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}
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*(uint32_t *)(d->config + address) = cpu_to_le32(val);
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pci_update_mappings(d);
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return;
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}
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@ -484,16 +503,16 @@ static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
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s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
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}
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static void PPC_PCIIO_writeb (target_phys_addr_t addr, uint32_t val)
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static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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set_config(s, addr);
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pci_data_write(s, addr, val, 1);
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}
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static void PPC_PCIIO_writew (target_phys_addr_t addr, uint32_t val)
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static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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set_config(s, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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@ -501,9 +520,9 @@ static void PPC_PCIIO_writew (target_phys_addr_t addr, uint32_t val)
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pci_data_write(s, addr, val, 2);
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}
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static void PPC_PCIIO_writel (target_phys_addr_t addr, uint32_t val)
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static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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set_config(s, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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@ -511,18 +530,18 @@ static void PPC_PCIIO_writel (target_phys_addr_t addr, uint32_t val)
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pci_data_write(s, addr, val, 4);
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}
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static uint32_t PPC_PCIIO_readb (target_phys_addr_t addr)
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static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 1);
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return val;
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}
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static uint32_t PPC_PCIIO_readw (target_phys_addr_t addr)
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static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 2);
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@ -532,9 +551,9 @@ static uint32_t PPC_PCIIO_readw (target_phys_addr_t addr)
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return val;
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}
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static uint32_t PPC_PCIIO_readl (target_phys_addr_t addr)
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static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 4);
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@ -558,10 +577,12 @@ static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
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void pci_prep_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *d;
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int PPC_io_memory;
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PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, PPC_PCIIO_write);
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PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
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PPC_PCIIO_write, s);
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cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
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d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0,
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@ -581,18 +602,18 @@ void pci_prep_init(void)
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/* pmac pci init */
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static void pci_pmac_config_writel (target_phys_addr_t addr, uint32_t val)
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static void pci_pmac_config_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->config_reg = val;
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}
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static uint32_t pci_pmac_config_readl (target_phys_addr_t addr)
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static uint32_t pci_pmac_config_readl (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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val = s->config_reg;
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@ -614,41 +635,41 @@ static CPUReadMemoryFunc *pci_pmac_config_read[] = {
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&pci_pmac_config_readl,
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};
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static void pci_pmac_writeb (target_phys_addr_t addr, uint32_t val)
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static void pci_pmac_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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pci_data_write(s, addr, val, 1);
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}
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static void pci_pmac_writew (target_phys_addr_t addr, uint32_t val)
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static void pci_pmac_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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pci_data_write(s, addr, val, 2);
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}
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static void pci_pmac_writel (target_phys_addr_t addr, uint32_t val)
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static void pci_pmac_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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pci_data_write(s, addr, val, 4);
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}
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static uint32_t pci_pmac_readb (target_phys_addr_t addr)
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static uint32_t pci_pmac_readb (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr, 1);
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return val;
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}
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static uint32_t pci_pmac_readw (target_phys_addr_t addr)
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static uint32_t pci_pmac_readw (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr, 2);
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#ifdef TARGET_WORDS_BIGENDIAN
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@ -657,9 +678,9 @@ static uint32_t pci_pmac_readw (target_phys_addr_t addr)
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return val;
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}
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static uint32_t pci_pmac_readl (target_phys_addr_t addr)
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static uint32_t pci_pmac_readl (void *opaque, target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIBridge *s = opaque;
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uint32_t val;
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val = pci_data_read(s, addr, 4);
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@ -683,12 +704,13 @@ static CPUReadMemoryFunc *pci_pmac_read[] = {
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void pci_pmac_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data;
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pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
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pci_pmac_config_write);
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pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write);
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pci_pmac_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write, s);
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cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
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cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
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@ -812,7 +834,7 @@ static void pci_info_device(PCIDevice *d)
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if (d->config[PCI_INTERRUPT_PIN] != 0) {
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printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
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}
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for(i = 0;i < 6; i++) {
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for(i = 0;i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (r->size != 0) {
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printf(" BAR%d: ", i);
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@ -934,13 +956,22 @@ static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
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{
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PCIIORegion *r;
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uint16_t cmd;
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uint32_t ofs;
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pci_config_writel(d, 0x10 + region_num * 4, addr);
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if ( region_num == PCI_ROM_SLOT ) {
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ofs = 0x30;
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}else{
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ofs = 0x10 + region_num * 4;
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}
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pci_config_writel(d, ofs, addr);
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r = &d->io_regions[region_num];
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/* enable memory mappings */
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cmd = pci_config_readw(d, PCI_COMMAND);
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if (r->type & PCI_ADDRESS_SPACE_IO)
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if ( region_num == PCI_ROM_SLOT )
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cmd |= 2;
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else if (r->type & PCI_ADDRESS_SPACE_IO)
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cmd |= 1;
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else
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cmd |= 2;
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@ -977,7 +1008,7 @@ static void pci_bios_init_device(PCIDevice *d)
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break;
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default:
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/* default memory mappings */
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for(i = 0; i < 6; i++) {
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (r->size) {
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if (r->type & PCI_ADDRESS_SPACE_IO)
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4
vl.h
4
vl.h
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@ -391,6 +391,8 @@ typedef struct PCIIORegion {
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PCIMapIORegionFunc *map_func;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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struct PCIDevice {
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/* PCI config space */
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uint8_t config[256];
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@ -399,7 +401,7 @@ struct PCIDevice {
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int bus_num;
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int devfn;
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char name[64];
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PCIIORegion io_regions[6];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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