hw/riscv: sifive_u: Hook a GPIO controller
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines. This hooks the exsiting SiFive GPIO model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -11,8 +11,9 @@
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) OTP (One-Time Programmable) memory with stored serial number
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* 5) GEM (Gigabit Ethernet Controller) and management block
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* 4) GPIO (General Purpose Input/Output Controller)
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* 5) OTP (One-Time Programmable) memory with stored serial number
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* 6) GEM (Gigabit Ethernet Controller) and management block
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts and up to five harts.
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@ -75,6 +76,7 @@ static const struct MemmapEntry {
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[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
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[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
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[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(cells);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/gpio@%lx",
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(long)memmap[SIFIVE_U_GPIO].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_TLCLK);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
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qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GPIO].base,
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0x0, memmap[SIFIVE_U_GPIO].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
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SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
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SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
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SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
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SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
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SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
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g_free(nodename);
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phy_phandle = phandle++;
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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@ -515,6 +539,7 @@ static void sifive_u_soc_instance_init(Object *obj)
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object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
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object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
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object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
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object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
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}
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static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
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@ -600,6 +625,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
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sysbus_realize(SYS_BUS_DEVICE(&s->prci), &err);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
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qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
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sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
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/* Pass all GPIOs to the SOC layer so they are available to the board */
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qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
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/* Connect GPIO interrupts to the PLIC */
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for (i = 0; i < 16; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
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qdev_get_gpio_in(DEVICE(s->plic),
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SIFIVE_U_GPIO_IRQ0 + i));
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}
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qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
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sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
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@ -22,6 +22,7 @@
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#include "hw/net/cadence_gem.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_cpu.h"
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#include "hw/riscv/sifive_gpio.h"
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#include "hw/riscv/sifive_u_prci.h"
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#include "hw/riscv/sifive_u_otp.h"
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@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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SiFiveUPRCIState prci;
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SIFIVEGPIOState gpio;
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SiFiveUOTPState otp;
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CadenceGEMState gem;
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@ -73,6 +75,7 @@ enum {
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SIFIVE_U_PRCI,
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SIFIVE_U_UART0,
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SIFIVE_U_UART1,
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SIFIVE_U_GPIO,
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SIFIVE_U_OTP,
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SIFIVE_U_FLASH0,
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SIFIVE_U_DRAM,
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@ -83,6 +86,22 @@ enum {
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enum {
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SIFIVE_U_UART0_IRQ = 4,
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SIFIVE_U_UART1_IRQ = 5,
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SIFIVE_U_GPIO_IRQ0 = 7,
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SIFIVE_U_GPIO_IRQ1 = 8,
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SIFIVE_U_GPIO_IRQ2 = 9,
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SIFIVE_U_GPIO_IRQ3 = 10,
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SIFIVE_U_GPIO_IRQ4 = 11,
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SIFIVE_U_GPIO_IRQ5 = 12,
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SIFIVE_U_GPIO_IRQ6 = 13,
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SIFIVE_U_GPIO_IRQ7 = 14,
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SIFIVE_U_GPIO_IRQ8 = 15,
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SIFIVE_U_GPIO_IRQ9 = 16,
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SIFIVE_U_GPIO_IRQ10 = 17,
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SIFIVE_U_GPIO_IRQ11 = 18,
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SIFIVE_U_GPIO_IRQ12 = 19,
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SIFIVE_U_GPIO_IRQ13 = 20,
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SIFIVE_U_GPIO_IRQ14 = 21,
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SIFIVE_U_GPIO_IRQ15 = 22,
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SIFIVE_U_GEM_IRQ = 0x35
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};
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