target-ppc: Add xvcv[hpsp, sphp] instructions
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision xvcvsphp: VSX Vector Convert Single Precision to Half Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2817,33 +2817,42 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
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/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
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* involving one half precision value
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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* stp - source type
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* ttp - target type
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* sfld - source vsr_t field
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* tfld - target vsr_t field
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* sfprf - set FPRF
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*/
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#define VSX_CVT_FP_TO_FP_HP(op, stp, ttp, sfld, tfld) \
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#define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xb; \
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int i; \
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\
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getVSR(xB(opcode), &xb, env); \
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memset(&xt, 0, sizeof(xt)); \
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\
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for (i = 0; i < nels; i++) { \
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xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb.sfld, \
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&env->fp_status))) { \
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
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xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
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} \
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if (sfprf) { \
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helper_compute_fprf_##ttp(env, xt.tfld); \
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} \
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} \
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\
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putVSR(xT(opcode), &xt, env); \
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float_check_status(env); \
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}
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VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
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VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
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VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
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VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
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VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
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VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
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/*
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* xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
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@ -536,6 +536,8 @@ DEF_HELPER_2(xvcmpgesp, void, env, i32)
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DEF_HELPER_2(xvcmpgtsp, void, env, i32)
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DEF_HELPER_2(xvcmpnesp, void, env, i32)
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DEF_HELPER_2(xvcvspdp, void, env, i32)
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DEF_HELPER_2(xvcvsphp, void, env, i32)
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DEF_HELPER_2(xvcvhpsp, void, env, i32)
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DEF_HELPER_2(xvcvspsxds, void, env, i32)
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DEF_HELPER_2(xvcvspsxws, void, env, i32)
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DEF_HELPER_2(xvcvspuxds, void, env, i32)
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@ -913,6 +913,8 @@ GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300)
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GEN_VSX_HELPER_2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300)
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GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
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@ -291,6 +291,8 @@ GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
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GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300),
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GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300),
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GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300),
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GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300),
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GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300),
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GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300),
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#define VSX_LOGICAL(name, opc2, opc3, fl2) \
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