target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16, LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -16733,6 +16733,14 @@ static inline int decode_gpr_gpr3(int r)
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return map[r & 0x7];
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return map[r & 0x7];
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}
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}
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/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3.src.store'). */
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static inline int decode_gpr_gpr3_src_store(int r)
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{
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static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 };
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return map[r & 0x7];
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}
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/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
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/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
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static inline int decode_gpr_gpr4(int r)
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static inline int decode_gpr_gpr4(int r)
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{
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{
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@ -16742,6 +16750,15 @@ static inline int decode_gpr_gpr4(int r)
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return map[r & 0xf];
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return map[r & 0xf];
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}
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}
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/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4.zero'). */
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static inline int decode_gpr_gpr4_zero(int r)
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{
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static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7,
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16, 17, 18, 19, 20, 21, 22, 23 };
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return map[r & 0xf];
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}
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static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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{
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@ -16749,6 +16766,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
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int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
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int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
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int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
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int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
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int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
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int offset;
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int imm;
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int imm;
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/* make sure instructions are on a halfword boundary */
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/* make sure instructions are on a halfword boundary */
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@ -16816,6 +16834,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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break;
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break;
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case NM_P16C:
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case NM_P16C:
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switch (ctx->opcode & 1) {
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case NM_POOL16C_0:
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break;
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case NM_LWXS16:
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gen_ldxs(ctx, rt, rs, rd);
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break;
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}
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break;
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break;
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case NM_P16_A1:
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case NM_P16_A1:
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switch (extract32(ctx->opcode, 6, 1)) {
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switch (extract32(ctx->opcode, 6, 1)) {
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@ -16887,24 +16912,95 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_ANDI16:
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case NM_ANDI16:
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break;
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break;
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case NM_P16_LB:
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case NM_P16_LB:
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offset = extract32(ctx->opcode, 0, 2);
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switch (extract32(ctx->opcode, 2, 2)) {
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case NM_LB16:
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gen_ld(ctx, OPC_LB, rt, rs, offset);
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break;
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case NM_SB16:
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rt = decode_gpr_gpr3_src_store(
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NANOMIPS_EXTRACT_RD(ctx->opcode));
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gen_st(ctx, OPC_SB, rt, rs, offset);
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break;
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case NM_LBU16:
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gen_ld(ctx, OPC_LBU, rt, rs, offset);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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break;
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case NM_P16_LH:
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case NM_P16_LH:
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offset = extract32(ctx->opcode, 1, 2) << 1;
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switch ((extract32(ctx->opcode, 3, 1) << 1) | (ctx->opcode & 1)) {
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case NM_LH16:
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gen_ld(ctx, OPC_LH, rt, rs, offset);
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break;
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case NM_SH16:
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rt = decode_gpr_gpr3_src_store(
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NANOMIPS_EXTRACT_RD(ctx->opcode));
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gen_st(ctx, OPC_SH, rt, rs, offset);
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break;
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case NM_LHU16:
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gen_ld(ctx, OPC_LHU, rt, rs, offset);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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break;
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case NM_LW16:
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case NM_LW16:
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offset = extract32(ctx->opcode, 0, 4) << 2;
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gen_ld(ctx, OPC_LW, rt, rs, offset);
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break;
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break;
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case NM_LWSP16:
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case NM_LWSP16:
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rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
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offset = extract32(ctx->opcode, 0, 5) << 2;
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gen_ld(ctx, OPC_LW, rt, 29, offset);
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break;
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break;
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case NM_LW4X4:
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case NM_LW4X4:
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rt = (extract32(ctx->opcode, 9, 1) << 3) |
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extract32(ctx->opcode, 5, 3);
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rs = (extract32(ctx->opcode, 4, 1) << 3) |
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extract32(ctx->opcode, 0, 3);
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offset = (extract32(ctx->opcode, 3, 1) << 3) |
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(extract32(ctx->opcode, 8, 1) << 2);
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rt = decode_gpr_gpr4(rt);
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rs = decode_gpr_gpr4(rs);
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gen_ld(ctx, OPC_LW, rt, rs, offset);
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break;
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break;
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case NM_SW4X4:
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case NM_SW4X4:
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rt = (extract32(ctx->opcode, 9, 1) << 3) |
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extract32(ctx->opcode, 5, 3);
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rs = (extract32(ctx->opcode, 4, 1) << 3) |
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extract32(ctx->opcode, 0, 3);
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offset = (extract32(ctx->opcode, 3, 1) << 3) |
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(extract32(ctx->opcode, 8, 1) << 2);
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rt = decode_gpr_gpr4_zero(rt);
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rs = decode_gpr_gpr4(rs);
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gen_st(ctx, OPC_SW, rt, rs, offset);
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break;
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break;
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case NM_LWGP16:
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case NM_LWGP16:
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offset = extract32(ctx->opcode, 0, 7) << 2;
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gen_ld(ctx, OPC_LW, rt, 28, offset);
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break;
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break;
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case NM_SWSP16:
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case NM_SWSP16:
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rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
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offset = extract32(ctx->opcode, 0, 5) << 2;
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gen_st(ctx, OPC_SW, rt, 29, offset);
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break;
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break;
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case NM_SW16:
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case NM_SW16:
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rt = decode_gpr_gpr3_src_store(
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NANOMIPS_EXTRACT_RD(ctx->opcode));
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rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
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offset = extract32(ctx->opcode, 0, 4) << 2;
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gen_st(ctx, OPC_SW, rt, rs, offset);
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break;
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break;
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case NM_SWGP16:
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case NM_SWGP16:
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rt = decode_gpr_gpr3_src_store(
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NANOMIPS_EXTRACT_RD(ctx->opcode));
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offset = extract32(ctx->opcode, 0, 7) << 2;
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gen_st(ctx, OPC_SW, rt, 28, offset);
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break;
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break;
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case NM_BC16:
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case NM_BC16:
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gen_compute_branch_nm(ctx, OPC_BEQ, 2, 0, 0,
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gen_compute_branch_nm(ctx, OPC_BEQ, 2, 0, 0,
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