ppc: Split pcr_mask settings into supported bits and the register mask
The current pcr_mask values are ambiguous: Should these be the mask that defines valid bits in the PCR register? Or should these rather indicate which compatibility levels are possible? Anyway, POWER6 and POWER7 should certainly not use the same values here. So let's introduce an additional variable "pcr_supported" here which is used to indicate the valid compatibility levels, and use pcr_mask to signal the valid bits in the PCR register. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -934,9 +934,9 @@ static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr,
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}
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}
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/* If it is a logical PVR, try to determine the highest level */
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/* If it is a logical PVR, try to determine the highest level */
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is205 = (pcc->pcr_mask & PCR_COMPAT_2_05) &&
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is205 = (pcc->pcr_supported & PCR_COMPAT_2_05) &&
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(lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05));
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(lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05));
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is206 = (pcc->pcr_mask & PCR_COMPAT_2_06) &&
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is206 = (pcc->pcr_supported & PCR_COMPAT_2_06) &&
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((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) ||
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((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) ||
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(lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS)));
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(lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS)));
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@ -165,7 +165,8 @@ typedef struct PowerPCCPUClass {
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uint32_t pvr;
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uint32_t pvr;
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bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
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bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
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uint64_t pcr_mask;
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uint64_t pcr_mask; /* Available bits in PCR register */
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uint64_t pcr_supported; /* Bits for supported PowerISA versions */
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uint32_t svr;
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uint32_t svr;
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uint64_t insns_flags;
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uint64_t insns_flags;
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uint64_t insns_flags2;
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uint64_t insns_flags2;
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@ -2200,6 +2200,7 @@ enum {
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enum {
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enum {
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PCR_COMPAT_2_05 = 1ull << (63-62),
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PCR_COMPAT_2_05 = 1ull << (63-62),
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PCR_COMPAT_2_06 = 1ull << (63-61),
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PCR_COMPAT_2_06 = 1ull << (63-61),
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PCR_COMPAT_2_07 = 1ull << (63-60),
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PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
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PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
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PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
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PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
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PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
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PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
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@ -8365,7 +8365,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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dc->desc = "POWER7";
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dc->desc = "POWER7";
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dc->props = powerpc_servercpu_properties;
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dc->props = powerpc_servercpu_properties;
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pcc->pvr_match = ppc_pvr_match_power7;
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pcc->pvr_match = ppc_pvr_match_power7;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
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pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
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pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
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pcc->init_proc = init_proc_POWER7;
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pcc->init_proc = init_proc_POWER7;
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pcc->check_pow = check_pow_nocheck;
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pcc->check_pow = check_pow_nocheck;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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@ -8445,7 +8446,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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dc->desc = "POWER8";
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dc->desc = "POWER8";
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dc->props = powerpc_servercpu_properties;
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dc->props = powerpc_servercpu_properties;
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pcc->pvr_match = ppc_pvr_match_power8;
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pcc->pvr_match = ppc_pvr_match_power8;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
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pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
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pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
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pcc->init_proc = init_proc_POWER8;
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pcc->init_proc = init_proc_POWER8;
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pcc->check_pow = check_pow_nocheck;
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pcc->check_pow = check_pow_nocheck;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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