target/mips: Fix some comment spelling errors
There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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/*
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/*
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* A MIPS configured with a vectorizing external interrupt controller
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* A MIPS configured with a vectorizing external interrupt controller
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* will feed a vector into the Cause pending lines. The core treats
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* will feed a vector into the Cause pending lines. The core treats
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* the status lines as a vector level, not as indiviual masks.
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* the status lines as a vector level, not as individual masks.
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*/
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*/
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r = pending > status;
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r = pending > status;
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} else {
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} else {
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@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
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t0 = tcg_temp_new();
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t0 = tcg_temp_new();
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addr = tcg_temp_new();
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addr = tcg_temp_new();
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/* compare the address against that of the preceeding LL */
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/* compare the address against that of the preceding LL */
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gen_base_offset_addr(ctx, addr, base, offset);
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gen_base_offset_addr(ctx, addr, base, offset);
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tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
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tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
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tcg_temp_free(addr);
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tcg_temp_free(addr);
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@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
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}
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}
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/* return resulting half-words to its original position */
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/* return resulting half-words to its original position */
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tcg_gen_shri_i32(t0, t0, 16);
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tcg_gen_shri_i32(t0, t0, 16);
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/* finaly update the destination */
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/* finally update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_temp_free(t1);
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tcg_temp_free(t1);
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@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
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}
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}
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/* return resulting half-words to its original position */
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/* return resulting half-words to its original position */
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tcg_gen_shri_i32(t0, t0, 16);
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tcg_gen_shri_i32(t0, t0, 16);
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/* finaly update the destination */
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/* finally update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_temp_free(t1);
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tcg_temp_free(t1);
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@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
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}
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}
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/* return resulting byte to its original position */
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/* return resulting byte to its original position */
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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/* finaly update the destination */
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/* finally update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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}
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}
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@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
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}
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}
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/* return resulting byte to its original position */
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/* return resulting byte to its original position */
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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/* finaly update the destination */
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/* finally update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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}
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}
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@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
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/* MVPConf1 implemented, TLB sharable, no gating storage support,
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/* MVPConf1 implemented, TLB sharable, no gating storage support,
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programmable cache partitioning implemented, number of allocatable
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programmable cache partitioning implemented, number of allocatable
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and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
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and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
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implemented, 5 TCs implemented. */
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implemented, 5 TCs implemented. */
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env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
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env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
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(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
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(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
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