ETRAX: Simplify the interrupt controller model.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
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@ -29,33 +29,33 @@
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#define D(x)
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#define D(x)
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#define R_RW_MASK 0
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#define R_R_VECT 1
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#define R_R_MASKED_VECT 2
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#define R_R_NMI 3
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#define R_R_GURU 4
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#define R_MAX 5
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struct fs_pic_state_t
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struct fs_pic_state_t
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{
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{
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CPUState *env;
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CPUState *env;
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uint32_t regs[R_MAX];
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uint32_t rw_mask;
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/* Active interrupt lines. */
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uint32_t r_vect;
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/* Active lines, gated through the mask. */
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uint32_t r_masked_vect;
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uint32_t r_nmi;
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uint32_t r_guru;
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};
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};
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static void pic_update(struct fs_pic_state_t *fs)
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static void pic_update(struct fs_pic_state_t *fs)
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{
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{
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CPUState *env = fs->env;
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CPUState *env = fs->env;
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int i;
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uint32_t vector = 0;
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uint32_t vector = 0;
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int i;
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fs->r_masked_vect = fs->r_vect & fs->rw_mask;
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
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/* The ETRAX interrupt controller signals interrupts to teh core
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/* The ETRAX interrupt controller signals interrupts to teh core
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through an interrupt request wire and an irq vector bus. If
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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0x30 and lets the sw choose the priorities. */
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if (fs->r_masked_vect) {
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if (fs->regs[R_R_MASKED_VECT]) {
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uint32_t mv = fs->r_masked_vect;
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uint32_t mv = fs->regs[R_R_MASKED_VECT];
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for (i = 0; i < 31; i++) {
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for (i = 0; i < 31; i++) {
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if (mv & 1) {
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if (mv & 1) {
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vector = 0x31 + i;
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vector = 0x31 + i;
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@ -83,28 +83,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
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struct fs_pic_state_t *fs = opaque;
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struct fs_pic_state_t *fs = opaque;
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uint32_t rval;
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uint32_t rval;
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switch (addr)
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rval = fs->regs[addr >> 2];
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{
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case 0x0:
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rval = fs->rw_mask;
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break;
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case 0x4:
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rval = fs->r_vect;
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break;
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case 0x8:
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rval = fs->r_masked_vect;
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break;
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case 0xc:
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rval = fs->r_nmi;
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break;
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case 0x10:
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rval = fs->r_guru;
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break;
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default:
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cpu_abort(fs->env, "invalid PIC register.\n");
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break;
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}
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D(printf("%s %x=%x\n", __func__, addr, rval));
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D(printf("%s %x=%x\n", __func__, addr, rval));
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return rval;
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return rval;
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}
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}
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@ -114,15 +93,10 @@ pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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{
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struct fs_pic_state_t *fs = opaque;
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struct fs_pic_state_t *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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switch (addr)
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{
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if (addr == R_RW_MASK) {
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case 0x0:
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fs->regs[R_RW_MASK] = value;
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fs->rw_mask = value;
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pic_update(fs);
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pic_update(fs);
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break;
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default:
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cpu_abort(fs->env, "invalid PIC register.\n");
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break;
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}
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}
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}
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}
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@ -147,14 +121,9 @@ void irq_info(Monitor *mon)
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static void irq_handler(void *opaque, int irq, int level)
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static void irq_handler(void *opaque, int irq, int level)
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{
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{
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struct fs_pic_state_t *fs = (void *)opaque;
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struct fs_pic_state_t *fs = (void *)opaque;
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D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n",
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__func__, irq, level,
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fs->rw_mask, fs->r_vect, fs->r_masked_vect));
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irq -= 1;
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irq -= 1;
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fs->r_vect &= ~(1 << irq);
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fs->regs[R_R_VECT] &= ~(1 << irq);
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fs->r_vect |= (!!level << irq);
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fs->regs[R_R_VECT] |= (!!level << irq);
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pic_update(fs);
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pic_update(fs);
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}
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}
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@ -167,11 +136,11 @@ static void nmi_handler(void *opaque, int irq, int level)
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mask = 1 << irq;
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mask = 1 << irq;
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if (level)
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if (level)
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fs->r_nmi |= mask;
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fs->regs[R_R_NMI] |= mask;
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else
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else
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fs->r_nmi &= ~mask;
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fs->regs[R_R_NMI] &= ~mask;
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if (fs->r_nmi)
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if (fs->regs[R_R_NMI])
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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else
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
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@ -180,9 +149,7 @@ static void nmi_handler(void *opaque, int irq, int level)
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static void guru_handler(void *opaque, int irq, int level)
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static void guru_handler(void *opaque, int irq, int level)
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{
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{
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struct fs_pic_state_t *fs = (void *)opaque;
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struct fs_pic_state_t *fs = (void *)opaque;
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CPUState *env = fs->env;
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cpu_abort(fs->env, "%s unsupported exception\n", __func__);
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cpu_abort(env, "%s unsupported exception\n", __func__);
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}
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}
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struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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@ -200,7 +167,7 @@ struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
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pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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cpu_register_physical_memory(base, 0x14, intr_vect_regs);
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cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
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return pic;
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return pic;
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}
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}
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