usb/hcd-xhci: Split pci wrapper for xhci base model
This patch sets the base to use xhci as sysbus model, for which pci specific hooks are moved to hcd-xhci-pci.c. As a part of this requirment msi/msix interrupts handling is moved under XHCIPCIState. Made required changes for qemu-xhci-nec. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Message-id: 1600957256-6494-4-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Sai Pavan Boddu
Gerd Hoffmann
parent
755fba11fb
commit
8ddab8dd3d
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@ -25,17 +25,17 @@
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "hcd-xhci.h"
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#include "hcd-xhci-pci.h"
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static Property nec_xhci_properties[] = {
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DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO),
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DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO),
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DEFINE_PROP_BIT("superspeed-ports-first",
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XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
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DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
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DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
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DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO),
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DEFINE_PROP_BIT("superspeed-ports-first", XHCIPciState,
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xhci.flags, XHCI_FLAG_SS_FIRST, true),
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DEFINE_PROP_BIT("force-pcie-endcap", XHCIPciState, xhci.flags,
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XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
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DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
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DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
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DEFINE_PROP_UINT32("intrs", XHCIPciState, xhci.numintrs, MAXINTRS),
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DEFINE_PROP_UINT32("slots", XHCIPciState, xhci.numslots, MAXSLOTS),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -52,7 +52,7 @@ static void nec_xhci_class_init(ObjectClass *klass, void *data)
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static const TypeInfo nec_xhci_info = {
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.name = TYPE_NEC_XHCI,
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.parent = TYPE_XHCI,
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.parent = TYPE_XHCI_PCI,
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.class_init = nec_xhci_class_init,
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};
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@ -25,12 +25,205 @@
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hcd-xhci.h"
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#include "hcd-xhci-pci.h"
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#include "trace.h"
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#include "qapi/error.h"
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#define OFF_MSIX_TABLE 0x3000
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#define OFF_MSIX_PBA 0x3800
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static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
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{
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XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
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PCIDevice *pci_dev = PCI_DEVICE(s);
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if (!msix_enabled(pci_dev)) {
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return;
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}
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if (enable == !!xhci->intr[n].msix_used) {
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return;
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}
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if (enable) {
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trace_usb_xhci_irq_msix_use(n);
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msix_vector_use(pci_dev, n);
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xhci->intr[n].msix_used = true;
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} else {
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trace_usb_xhci_irq_msix_unuse(n);
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msix_vector_unuse(pci_dev, n);
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xhci->intr[n].msix_used = false;
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}
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}
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static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
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{
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XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
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PCIDevice *pci_dev = PCI_DEVICE(s);
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if (n == 0 &&
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!(msix_enabled(pci_dev) ||
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msi_enabled(pci_dev))) {
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pci_set_irq(pci_dev, level);
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}
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if (msix_enabled(pci_dev)) {
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msix_notify(pci_dev, n);
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return;
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}
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if (msi_enabled(pci_dev)) {
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msi_notify(pci_dev, n);
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return;
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}
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}
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static void xhci_pci_reset(DeviceState *dev)
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{
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XHCIPciState *s = XHCI_PCI(dev);
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device_legacy_reset(DEVICE(&s->xhci));
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}
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static int xhci_pci_vmstate_post_load(void *opaque, int version_id)
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{
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XHCIPciState *s = XHCI_PCI(opaque);
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PCIDevice *pci_dev = PCI_DEVICE(s);
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int intr;
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for (intr = 0; intr < s->xhci.numintrs; intr++) {
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if (s->xhci.intr[intr].msix_used) {
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msix_vector_use(pci_dev, intr);
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} else {
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msix_vector_unuse(pci_dev, intr);
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}
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}
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return 0;
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}
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static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
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{
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int ret;
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Error *err = NULL;
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XHCIPciState *s = XHCI_PCI(dev);
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dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
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dev->config[0x60] = 0x30; /* release number */
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object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
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s->xhci.intr_update = xhci_pci_intr_update;
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s->xhci.intr_raise = xhci_pci_intr_raise;
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object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
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s->xhci.nec_quirks = true;
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}
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if (s->msi != ON_OFF_AUTO_OFF) {
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ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
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/*
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* Any error other than -ENOTSUP(board's MSI support is broken)
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* is a programming error
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*/
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assert(!ret || ret == -ENOTSUP);
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if (ret && s->msi == ON_OFF_AUTO_ON) {
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/* Can't satisfy user's explicit msi=on request, fail */
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error_append_hint(&err, "You have to use msi=auto (default) or "
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"msi=off with this machine type.\n");
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error_propagate(errp, err);
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return;
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}
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assert(!err || s->msi == ON_OFF_AUTO_AUTO);
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/* With msi=auto, we fall back to MSI off silently */
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error_free(err);
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}
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pci_register_bar(dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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&s->xhci.mem);
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if (pci_bus_is_express(pci_get_bus(dev)) ||
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xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
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ret = pcie_endpoint_cap_init(dev, 0xa0);
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assert(ret > 0);
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}
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if (s->msix != ON_OFF_AUTO_OFF) {
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/* TODO check for errors, and should fail when msix=on */
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msix_init(dev, s->xhci.numintrs,
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&s->xhci.mem, 0, OFF_MSIX_TABLE,
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&s->xhci.mem, 0, OFF_MSIX_PBA,
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0x90, NULL);
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}
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s->xhci.as = pci_get_address_space(dev);
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}
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static void usb_xhci_pci_exit(PCIDevice *dev)
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{
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XHCIPciState *s = XHCI_PCI(dev);
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/* destroy msix memory region */
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if (dev->msix_table && dev->msix_pba
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&& dev->msix_entry_used) {
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msix_uninit(dev, &s->xhci.mem, &s->xhci.mem);
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}
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}
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static const VMStateDescription vmstate_xhci_pci = {
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.name = "xhci",
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.version_id = 1,
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.post_load = xhci_pci_vmstate_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState),
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VMSTATE_MSIX(parent_obj, XHCIPciState),
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VMSTATE_STRUCT(xhci, XHCIPciState, 1, vmstate_xhci, XHCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xhci_instance_init(Object *obj)
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{
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XHCIPciState *s = XHCI_PCI(obj);
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/*
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* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
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* line, therefore, no need to wait to realize like other devices
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*/
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PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
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object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
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qdev_alias_all_properties(DEVICE(&s->xhci), obj);
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}
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static void xhci_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = xhci_pci_reset;
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dc->vmsd = &vmstate_xhci_pci;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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k->realize = usb_xhci_pci_realize;
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k->exit = usb_xhci_pci_exit;
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k->class_id = PCI_CLASS_SERIAL_USB;
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}
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static const TypeInfo xhci_pci_info = {
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.name = TYPE_XHCI_PCI,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(XHCIPciState),
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.class_init = xhci_class_init,
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.instance_init = xhci_instance_init,
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.abstract = true,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ }
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},
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};
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static void qemu_xhci_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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@ -42,10 +235,11 @@ static void qemu_xhci_class_init(ObjectClass *klass, void *data)
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static void qemu_xhci_instance_init(Object *obj)
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{
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XHCIState *xhci = XHCI(obj);
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XHCIPciState *s = XHCI_PCI(obj);
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XHCIState *xhci = &s->xhci;
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xhci->msi = ON_OFF_AUTO_OFF;
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xhci->msix = ON_OFF_AUTO_AUTO;
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s->msi = ON_OFF_AUTO_OFF;
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s->msix = ON_OFF_AUTO_AUTO;
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xhci->numintrs = MAXINTRS;
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xhci->numslots = MAXSLOTS;
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xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
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@ -53,13 +247,14 @@ static void qemu_xhci_instance_init(Object *obj)
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static const TypeInfo qemu_xhci_info = {
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.name = TYPE_QEMU_XHCI,
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.parent = TYPE_XHCI,
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.parent = TYPE_XHCI_PCI,
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.class_init = qemu_xhci_class_init,
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.instance_init = qemu_xhci_instance_init,
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};
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static void xhci_register_types(void)
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{
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type_register_static(&xhci_pci_info);
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type_register_static(&qemu_xhci_info);
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}
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44
hw/usb/hcd-xhci-pci.h
Normal file
44
hw/usb/hcd-xhci-pci.h
Normal file
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@ -0,0 +1,44 @@
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/*
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* USB xHCI controller emulation
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*
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* Copyright (c) 2011 Securiforest
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* Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
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* Based on usb-ohci.c, emulates Renesas NEC USB 3.0
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* Date: 2020-01-1; Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
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* PCI hooks are moved from XHCIState to XHCIPciState
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_USB_HCD_XHCI_PCI_H
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#define HW_USB_HCD_XHCI_PCI_H
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#include "hw/usb.h"
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#include "hcd-xhci.h"
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#define TYPE_XHCI_PCI "pci-xhci"
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#define XHCI_PCI(obj) \
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OBJECT_CHECK(XHCIPciState, (obj), TYPE_XHCI_PCI)
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typedef struct XHCIPciState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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XHCIState xhci;
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OnOffAuto msi;
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OnOffAuto msix;
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} XHCIPciState;
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#endif
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@ -24,10 +24,7 @@
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#include "qemu/module.h"
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#include "qemu/queue.h"
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#include "migration/vmstate.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "trace.h"
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#include "qapi/error.h"
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@ -56,8 +53,6 @@
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#define OFF_OPER LEN_CAP
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#define OFF_RUNTIME 0x1000
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#define OFF_DOORBELL 0x2000
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#define OFF_MSIX_TABLE 0x3000
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#define OFF_MSIX_PBA 0x3800
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/* must be power of 2 */
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#define LEN_REGS 0x4000
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@ -547,54 +542,28 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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return &xhci->ports[index];
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}
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static void xhci_intx_update(XHCIState *xhci)
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static void xhci_intr_update(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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int level = 0;
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if (msix_enabled(pci_dev) ||
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msi_enabled(pci_dev)) {
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return;
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if (v == 0) {
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if (xhci->intr[0].iman & IMAN_IP &&
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xhci->intr[0].iman & IMAN_IE &&
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xhci->usbcmd & USBCMD_INTE) {
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level = 1;
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}
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if (xhci->intr_raise) {
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xhci->intr_raise(xhci, 0, level);
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}
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}
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if (xhci->intr[0].iman & IMAN_IP &&
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xhci->intr[0].iman & IMAN_IE &&
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xhci->usbcmd & USBCMD_INTE) {
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level = 1;
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}
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trace_usb_xhci_irq_intx(level);
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pci_set_irq(pci_dev, level);
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}
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static void xhci_msix_update(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool enabled;
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if (!msix_enabled(pci_dev)) {
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return;
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}
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enabled = xhci->intr[v].iman & IMAN_IE;
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if (enabled == xhci->intr[v].msix_used) {
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return;
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}
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if (enabled) {
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trace_usb_xhci_irq_msix_use(v);
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msix_vector_use(pci_dev, v);
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xhci->intr[v].msix_used = true;
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} else {
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trace_usb_xhci_irq_msix_unuse(v);
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msix_vector_unuse(pci_dev, v);
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xhci->intr[v].msix_used = false;
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if (xhci->intr_update) {
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xhci->intr_update(xhci, v,
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xhci->intr[v].iman & IMAN_IE);
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}
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}
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static void xhci_intr_raise(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
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xhci->intr[v].erdp_low |= ERDP_EHB;
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@ -611,22 +580,8 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
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if (!(xhci->usbcmd & USBCMD_INTE)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (msix_enabled(pci_dev)) {
|
||||
trace_usb_xhci_irq_msix(v);
|
||||
msix_notify(pci_dev, v);
|
||||
return;
|
||||
}
|
||||
|
||||
if (msi_enabled(pci_dev)) {
|
||||
trace_usb_xhci_irq_msi(v);
|
||||
msi_notify(pci_dev, v);
|
||||
return;
|
||||
}
|
||||
|
||||
if (v == 0) {
|
||||
trace_usb_xhci_irq_intx(1);
|
||||
pci_irq_assert(pci_dev);
|
||||
if (xhci->intr_raise) {
|
||||
xhci->intr_raise(xhci, v, true);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2717,7 +2672,6 @@ static void xhci_reset(DeviceState *dev)
|
|||
xhci->intr[i].erstba_high = 0;
|
||||
xhci->intr[i].erdp_low = 0;
|
||||
xhci->intr[i].erdp_high = 0;
|
||||
xhci->intr[i].msix_used = 0;
|
||||
|
||||
xhci->intr[i].er_ep_idx = 0;
|
||||
xhci->intr[i].er_pcs = 1;
|
||||
|
|
@ -2939,8 +2893,7 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
|
|||
static void xhci_oper_write(void *ptr, hwaddr reg,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
XHCIState *xhci = ptr;
|
||||
DeviceState *d = DEVICE(ptr);
|
||||
XHCIState *xhci = XHCI(ptr);
|
||||
|
||||
trace_usb_xhci_oper_write(reg, val);
|
||||
|
||||
|
|
@ -2962,15 +2915,15 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
|
|||
xhci->usbcmd = val & 0xc0f;
|
||||
xhci_mfwrap_update(xhci);
|
||||
if (val & USBCMD_HCRST) {
|
||||
xhci_reset(d);
|
||||
xhci_reset(DEVICE(xhci));
|
||||
}
|
||||
xhci_intx_update(xhci);
|
||||
xhci_intr_update(xhci, 0);
|
||||
break;
|
||||
|
||||
case 0x04: /* USBSTS */
|
||||
/* these bits are write-1-to-clear */
|
||||
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
|
||||
xhci_intx_update(xhci);
|
||||
xhci_intr_update(xhci, 0);
|
||||
break;
|
||||
|
||||
case 0x14: /* DNCTRL */
|
||||
|
|
@ -3073,10 +3026,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
|
|||
}
|
||||
intr->iman &= ~IMAN_IE;
|
||||
intr->iman |= val & IMAN_IE;
|
||||
if (v == 0) {
|
||||
xhci_intx_update(xhci);
|
||||
}
|
||||
xhci_msix_update(xhci, v);
|
||||
xhci_intr_update(xhci, v);
|
||||
break;
|
||||
case 0x04: /* IMOD */
|
||||
intr->imod = val;
|
||||
|
|
@ -3321,7 +3271,6 @@ static USBBusOps xhci_bus_ops = {
|
|||
|
||||
static void usb_xhci_init(XHCIState *xhci)
|
||||
{
|
||||
DeviceState *dev = DEVICE(xhci);
|
||||
XHCIPort *port;
|
||||
unsigned int i, usbports, speedmask;
|
||||
|
||||
|
|
@ -3336,7 +3285,7 @@ static void usb_xhci_init(XHCIState *xhci)
|
|||
usbports = MAX(xhci->numports_2, xhci->numports_3);
|
||||
xhci->numports = xhci->numports_2 + xhci->numports_3;
|
||||
|
||||
usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
|
||||
usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
|
||||
|
||||
for (i = 0; i < usbports; i++) {
|
||||
speedmask = 0;
|
||||
|
|
@ -3376,21 +3325,12 @@ static void usb_xhci_init(XHCIState *xhci)
|
|||
}
|
||||
}
|
||||
|
||||
static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
|
||||
static void usb_xhci_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
int i, ret;
|
||||
Error *err = NULL;
|
||||
int i;
|
||||
|
||||
XHCIState *xhci = XHCI(dev);
|
||||
|
||||
dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
|
||||
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
|
||||
dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
|
||||
dev->config[0x60] = 0x30; /* release number */
|
||||
|
||||
if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
|
||||
xhci->nec_quirks = true;
|
||||
}
|
||||
if (xhci->numintrs > MAXINTRS) {
|
||||
xhci->numintrs = MAXINTRS;
|
||||
}
|
||||
|
|
@ -3412,36 +3352,18 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
|
|||
xhci->max_pstreams_mask = 0;
|
||||
}
|
||||
|
||||
if (xhci->msi != ON_OFF_AUTO_OFF) {
|
||||
ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
|
||||
/* Any error other than -ENOTSUP(board's MSI support is broken)
|
||||
* is a programming error */
|
||||
assert(!ret || ret == -ENOTSUP);
|
||||
if (ret && xhci->msi == ON_OFF_AUTO_ON) {
|
||||
/* Can't satisfy user's explicit msi=on request, fail */
|
||||
error_append_hint(&err, "You have to use msi=auto (default) or "
|
||||
"msi=off with this machine type.\n");
|
||||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
|
||||
/* With msi=auto, we fall back to MSI off silently */
|
||||
error_free(err);
|
||||
}
|
||||
|
||||
usb_xhci_init(xhci);
|
||||
xhci->as = pci_get_address_space(dev);
|
||||
xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
|
||||
|
||||
memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
|
||||
memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
|
||||
memory_region_init(&xhci->mem, OBJECT(dev), "xhci", LEN_REGS);
|
||||
memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
|
||||
"capabilities", LEN_CAP);
|
||||
memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
|
||||
memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
|
||||
"operational", 0x400);
|
||||
memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
|
||||
"runtime", LEN_RUNTIME);
|
||||
memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
|
||||
"doorbell", LEN_DOORBELL);
|
||||
memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
|
||||
xhci, "runtime", LEN_RUNTIME);
|
||||
memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
|
||||
xhci, "doorbell", LEN_DOORBELL);
|
||||
|
||||
memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
|
||||
memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
|
||||
|
|
@ -3452,31 +3374,13 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
|
|||
XHCIPort *port = &xhci->ports[i];
|
||||
uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
|
||||
port->xhci = xhci;
|
||||
memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
|
||||
memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
|
||||
port->name, 0x10);
|
||||
memory_region_add_subregion(&xhci->mem, offset, &port->mem);
|
||||
}
|
||||
|
||||
pci_register_bar(dev, 0,
|
||||
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
|
||||
&xhci->mem);
|
||||
|
||||
if (pci_bus_is_express(pci_get_bus(dev)) ||
|
||||
xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
|
||||
ret = pcie_endpoint_cap_init(dev, 0xa0);
|
||||
assert(ret > 0);
|
||||
}
|
||||
|
||||
if (xhci->msix != ON_OFF_AUTO_OFF) {
|
||||
/* TODO check for errors, and should fail when msix=on */
|
||||
msix_init(dev, xhci->numintrs,
|
||||
&xhci->mem, 0, OFF_MSIX_TABLE,
|
||||
&xhci->mem, 0, OFF_MSIX_PBA,
|
||||
0x90, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static void usb_xhci_exit(PCIDevice *dev)
|
||||
static void usb_xhci_unrealize(DeviceState *dev)
|
||||
{
|
||||
int i;
|
||||
XHCIState *xhci = XHCI(dev);
|
||||
|
|
@ -3503,25 +3407,18 @@ static void usb_xhci_exit(PCIDevice *dev)
|
|||
memory_region_del_subregion(&xhci->mem, &port->mem);
|
||||
}
|
||||
|
||||
/* destroy msix memory region */
|
||||
if (dev->msix_table && dev->msix_pba
|
||||
&& dev->msix_entry_used) {
|
||||
msix_uninit(dev, &xhci->mem, &xhci->mem);
|
||||
}
|
||||
|
||||
usb_bus_release(&xhci->bus);
|
||||
}
|
||||
|
||||
static int usb_xhci_post_load(void *opaque, int version_id)
|
||||
{
|
||||
XHCIState *xhci = opaque;
|
||||
PCIDevice *pci_dev = PCI_DEVICE(xhci);
|
||||
XHCISlot *slot;
|
||||
XHCIEPContext *epctx;
|
||||
dma_addr_t dcbaap, pctx;
|
||||
uint32_t slot_ctx[4];
|
||||
uint32_t ep_ctx[5];
|
||||
int slotid, epid, state, intr;
|
||||
int slotid, epid, state;
|
||||
|
||||
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
|
||||
|
||||
|
|
@ -3559,15 +3456,6 @@ static int usb_xhci_post_load(void *opaque, int version_id)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (intr = 0; intr < xhci->numintrs; intr++) {
|
||||
if (xhci->intr[intr].msix_used) {
|
||||
msix_vector_use(pci_dev, intr);
|
||||
} else {
|
||||
msix_vector_unuse(pci_dev, intr);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -3652,14 +3540,11 @@ static const VMStateDescription vmstate_xhci_intr = {
|
|||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_xhci = {
|
||||
.name = "xhci",
|
||||
const VMStateDescription vmstate_xhci = {
|
||||
.name = "xhci-core",
|
||||
.version_id = 1,
|
||||
.post_load = usb_xhci_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_PCI_DEVICE(parent_obj, XHCIState),
|
||||
VMSTATE_MSIX(parent_obj, XHCIState),
|
||||
|
||||
VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
|
||||
vmstate_xhci_port, XHCIPort),
|
||||
VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
|
||||
|
|
@ -3691,42 +3576,27 @@ static Property xhci_properties[] = {
|
|||
XHCI_FLAG_ENABLE_STREAMS, true),
|
||||
DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
|
||||
DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
|
||||
DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,
|
||||
DeviceState *),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void xhci_instance_init(Object *obj)
|
||||
{
|
||||
/* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
|
||||
* line, therefore, no need to wait to realize like other devices */
|
||||
PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
|
||||
}
|
||||
|
||||
static void xhci_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->vmsd = &vmstate_xhci;
|
||||
device_class_set_props(dc, xhci_properties);
|
||||
dc->realize = usb_xhci_realize;
|
||||
dc->unrealize = usb_xhci_unrealize;
|
||||
dc->reset = xhci_reset;
|
||||
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
||||
k->realize = usb_xhci_realize;
|
||||
k->exit = usb_xhci_exit;
|
||||
k->class_id = PCI_CLASS_SERIAL_USB;
|
||||
device_class_set_props(dc, xhci_properties);
|
||||
dc->user_creatable = false;
|
||||
}
|
||||
|
||||
static const TypeInfo xhci_info = {
|
||||
.name = TYPE_XHCI,
|
||||
.parent = TYPE_PCI_DEVICE,
|
||||
.parent = TYPE_DEVICE,
|
||||
.instance_size = sizeof(XHCIState),
|
||||
.class_init = xhci_class_init,
|
||||
.instance_init = xhci_instance_init,
|
||||
.abstract = true,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ INTERFACE_PCIE_DEVICE },
|
||||
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static void xhci_register_types(void)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include "qom/object.h"
|
||||
|
||||
#include "hw/usb.h"
|
||||
#include "sysemu/dma.h"
|
||||
|
||||
#define TYPE_XHCI "base-xhci"
|
||||
#define TYPE_NEC_XHCI "nec-usb-xhci"
|
||||
|
|
@ -183,10 +184,8 @@ typedef struct XHCIInterrupter {
|
|||
|
||||
} XHCIInterrupter;
|
||||
|
||||
struct XHCIState {
|
||||
/*< private >*/
|
||||
PCIDevice parent_obj;
|
||||
/*< public >*/
|
||||
typedef struct XHCIState {
|
||||
DeviceState parent;
|
||||
|
||||
USBBus bus;
|
||||
MemoryRegion mem;
|
||||
|
|
@ -203,8 +202,9 @@ struct XHCIState {
|
|||
uint32_t numslots;
|
||||
uint32_t flags;
|
||||
uint32_t max_pstreams_mask;
|
||||
OnOffAuto msi;
|
||||
OnOffAuto msix;
|
||||
void (*intr_update)(XHCIState *s, int n, bool enable);
|
||||
void (*intr_raise)(XHCIState *s, int n, bool level);
|
||||
DeviceState *hostOpaque;
|
||||
|
||||
/* Operational Registers */
|
||||
uint32_t usbcmd;
|
||||
|
|
@ -229,8 +229,9 @@ struct XHCIState {
|
|||
XHCIRing cmd_ring;
|
||||
|
||||
bool nec_quirks;
|
||||
};
|
||||
} XHCIState;
|
||||
|
||||
extern const VMStateDescription vmstate_xhci;
|
||||
bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit);
|
||||
void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue