target/xtensa: move WINDOW_BASE SR update to postprocessing
Opcodes that modify WINDOW_BASE SR don't have dependency on opcodes that use windowed registers. If such opcodes are combined in a single instruction they may not be correctly ordered. Instead of adding said dependency use temporary register to store changed WINDOW_BASE value and do actual register window rotation as a postprocessing step. Not all opcodes that change WINDOW_BASE need this: retw, rfwo and rfwu are also jump opcodes, so they are guaranteed to be translated last and thus will not affect other opcodes in the same instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -486,6 +486,7 @@ typedef struct CPUXtensaState {
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float64 f64;
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} fregs[16];
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float_status fp_status;
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uint32_t windowbase_next;
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#ifndef CONFIG_USER_ONLY
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xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
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@ -3,12 +3,11 @@ DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
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DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
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DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
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DEF_HELPER_2(wsr_windowbase, void, env, i32)
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DEF_HELPER_1(sync_windowbase, void, env)
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DEF_HELPER_4(entry, void, env, i32, i32, i32)
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DEF_HELPER_2(test_ill_retw, void, env, i32)
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DEF_HELPER_2(test_underflow_retw, void, env, i32)
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DEF_HELPER_2(retw, i32, env, i32)
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DEF_HELPER_2(rotw, void, env, i32)
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DEF_HELPER_3(window_check, noreturn, env, i32, i32)
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DEF_HELPER_1(restore_owb, void, env)
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DEF_HELPER_2(movsp, void, env, i32)
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@ -82,6 +82,7 @@ static TCGv_i32 cpu_R[16];
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static TCGv_i32 cpu_FR[16];
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static TCGv_i32 cpu_SR[256];
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static TCGv_i32 cpu_UR[256];
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static TCGv_i32 cpu_windowbase_next;
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#include "exec/gen-icount.h"
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@ -253,6 +254,11 @@ void xtensa_translate_init(void)
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uregnames[i].name);
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}
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}
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cpu_windowbase_next =
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tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUXtensaState, windowbase_next),
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"windowbase_next");
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}
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static inline bool option_enabled(DisasContext *dc, int opt)
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@ -557,7 +563,7 @@ static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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#ifndef CONFIG_USER_ONLY
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static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
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{
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gen_helper_wsr_windowbase(cpu_env, v);
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tcg_gen_mov_i32(cpu_windowbase_next, v);
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}
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static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
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@ -859,6 +865,9 @@ static int gen_postprocess(DisasContext *dc, int slot)
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if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
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gen_check_interrupts(dc);
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}
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if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
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gen_helper_sync_windowbase(cpu_env);
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}
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if (op_flags & XTENSA_OP_EXIT_TB_M1) {
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slot = -1;
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}
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@ -2268,9 +2277,7 @@ static void translate_rfw(DisasContext *dc, const uint32_t arg[],
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static void translate_rotw(DisasContext *dc, const uint32_t arg[],
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const uint32_t par[])
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{
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TCGv_i32 tmp = tcg_const_i32(arg[0]);
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gen_helper_rotw(cpu_env, tmp);
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tcg_temp_free(tmp);
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tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0]);
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}
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static void translate_rsil(DisasContext *dc, const uint32_t arg[],
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@ -2972,7 +2979,8 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_entry,
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.test_ill = test_ill_entry,
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.test_overflow = test_overflow_entry,
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.op_flags = XTENSA_OP_EXIT_TB_M1,
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.op_flags = XTENSA_OP_EXIT_TB_M1 |
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XTENSA_OP_SYNC_REGISTER_WINDOW,
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}, {
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.name = "esync",
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.translate = translate_nop,
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@ -3554,7 +3562,9 @@ static const XtensaOpcodeOps core_ops[] = {
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}, {
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.name = "rotw",
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.translate = translate_rotw,
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.op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
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.op_flags = XTENSA_OP_PRIVILEGED |
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XTENSA_OP_EXIT_TB_M1 |
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XTENSA_OP_SYNC_REGISTER_WINDOW,
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}, {
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.name = "rsil",
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.translate = translate_rsil,
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@ -4622,7 +4632,9 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_wsr,
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.test_ill = test_ill_wsr,
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.par = (const uint32_t[]){WINDOW_BASE},
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.op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
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.op_flags = XTENSA_OP_PRIVILEGED |
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XTENSA_OP_EXIT_TB_M1 |
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XTENSA_OP_SYNC_REGISTER_WINDOW,
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}, {
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.name = "wsr.windowstart",
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.translate = translate_wsr,
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@ -5108,7 +5120,9 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_xsr,
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.test_ill = test_ill_xsr,
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.par = (const uint32_t[]){WINDOW_BASE},
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.op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
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.op_flags = XTENSA_OP_PRIVILEGED |
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XTENSA_OP_EXIT_TB_M1 |
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XTENSA_OP_SYNC_REGISTER_WINDOW,
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}, {
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.name = "xsr.windowstart",
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.translate = translate_xsr,
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@ -96,9 +96,9 @@ void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta)
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xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
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}
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void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
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void HELPER(sync_windowbase)(CPUXtensaState *env)
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{
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xtensa_rotate_window_abs(env, v);
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xtensa_rotate_window_abs(env, env->windowbase_next);
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}
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void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
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@ -106,9 +106,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
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int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
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xtensa_rotate_window(env, callinc);
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env->sregs[WINDOW_START] |=
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windowstart_bit(env->sregs[WINDOW_BASE], env);
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env->windowbase_next = env->sregs[WINDOW_BASE] + callinc;
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env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env);
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}
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void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
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@ -196,11 +195,6 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
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return ret_pc;
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}
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void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
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{
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xtensa_rotate_window(env, imm4);
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}
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void xtensa_restore_owb(CPUXtensaState *env)
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{
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xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
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