serial: Convert serial_mm_init to MemoryRegion
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
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parent
06dccb82df
commit
8e8ffc44e8
145
hw/serial.c
145
hw/serial.c
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@ -28,6 +28,7 @@
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#include "pc.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "exec-memory.h"
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//#define DEBUG_SERIAL
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@ -153,11 +154,11 @@ struct SerialState {
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int poll_msl;
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struct QEMUTimer *modem_status_poll;
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MemoryRegion io;
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};
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typedef struct ISASerialState {
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ISADevice dev;
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MemoryRegion io;
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uint32_t index;
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uint32_t iobase;
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uint32_t isairq;
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@ -786,8 +787,8 @@ static int serial_isa_initfn(ISADevice *dev)
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serial_init_core(s);
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qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
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memory_region_init_io(&isa->io, &serial_io_ops, s, "serial", 8);
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isa_register_ioport(dev, &isa->io, isa->iobase);
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memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
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isa_register_ioport(dev, &s->io, isa->iobase);
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return 0;
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}
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@ -821,115 +822,37 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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}
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/* Memory mapped interface */
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static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
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static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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SerialState *s = opaque;
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return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
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return serial_ioport_read(s, addr >> s->it_shift);
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}
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static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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static void serial_mm_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
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}
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static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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uint32_t val;
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val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
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val = bswap16(val);
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return val;
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}
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static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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uint32_t val;
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val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
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return val;
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}
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static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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SerialState *s = opaque;
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value = bswap16(value);
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serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
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}
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static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
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}
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static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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uint32_t val;
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val = serial_ioport_read(s, addr >> s->it_shift);
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val = bswap32(val);
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return val;
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}
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static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
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{
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SerialState *s = opaque;
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uint32_t val;
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val = serial_ioport_read(s, addr >> s->it_shift);
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return val;
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}
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static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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SerialState *s = opaque;
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value = bswap32(value);
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value &= ~0u >> (32 - (size * 8));
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serial_ioport_write(s, addr >> s->it_shift, value);
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}
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static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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SerialState *s = opaque;
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serial_ioport_write(s, addr >> s->it_shift, value);
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}
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static CPUReadMemoryFunc * const serial_mm_read_be[] = {
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&serial_mm_readb,
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&serial_mm_readw_be,
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&serial_mm_readl_be,
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};
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static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
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&serial_mm_writeb,
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&serial_mm_writew_be,
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&serial_mm_writel_be,
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};
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static CPUReadMemoryFunc * const serial_mm_read_le[] = {
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&serial_mm_readb,
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&serial_mm_readw_le,
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&serial_mm_readl_le,
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};
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static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
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&serial_mm_writeb,
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&serial_mm_writew_le,
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&serial_mm_writel_le,
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static const MemoryRegionOps serial_mm_ops[3] = {
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[DEVICE_NATIVE_ENDIAN] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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},
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[DEVICE_LITTLE_ENDIAN] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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},
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[DEVICE_BIG_ENDIAN] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_BIG_ENDIAN,
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},
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};
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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@ -938,7 +861,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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int be)
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{
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SerialState *s;
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int s_io_memory;
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enum device_endian end;
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s = g_malloc0(sizeof(SerialState));
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@ -950,17 +873,11 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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serial_init_core(s);
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vmstate_register(NULL, base, &vmstate_serial, s);
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end = (be ? DEVICE_BIG_ENDIAN : DEVICE_LITTLE_ENDIAN);
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memory_region_init_io(&s->io, &serial_mm_ops[end], s,
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"serial", 8 << it_shift);
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if (ioregister) {
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if (be) {
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s_io_memory = cpu_register_io_memory(serial_mm_read_be,
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serial_mm_write_be, s,
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DEVICE_NATIVE_ENDIAN);
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} else {
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s_io_memory = cpu_register_io_memory(serial_mm_read_le,
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serial_mm_write_le, s,
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DEVICE_NATIVE_ENDIAN);
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}
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cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
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memory_region_add_subregion(get_system_memory(), base, &s->io);
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}
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serial_update_msl(s);
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return s;
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