target/xtensa: preparation for FLIX support
Separate generation of per-instruction code (such as raising exceptions and terminating TB) from per-opcode code. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAluyZAoTHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRO/JD/0bTPxmqU/8svhNLdlG7woSICG4T/z3 DIhttiedDqtLBVKpmziqFtC7EK5Mo/Pydpo5R0jxsLUvxuBSHwnlPUdixzrA5L/t GY9Xr1VLdjjv2C8i/9SUyIRswMutp++Gxy4DNi93oqBoaxh5fbcMmWEa4CVApn6m /7z6MHiVUVtuS3HXqs7uvDl8fKv4//CISMpVRNhZ9aTp99/Oc+Xiwlmg/Gl4SNCG 1RMI6UzFy0CYfzwZr9YRO58wvWTH5mv+YoYkXsMKiQ2MFYZ5/SWhi7bzANXsMGgh u5oFfwbJa6o5//3EHeohmdwg8vuyOMasE352Sx//sSxgVFheBEoU21qJdujQiyKU 2RNpVWDHd7JTP+nlGvIrc/kpZmVYirn9YUi64S9CunCLrPHTKIexrXHpr7QxS+Pk zWcrAAehzZ7nM4R1VWWWcg2g9FECLT+Nuqpvsr3JFJ+fXT7mjgKvDAMuUV+SnYFx 514Jx0epsoVdbDB7PIwn8J3liiPRfHGiCHew6ZU8OBMBCqnOcTc/l7Ibqcnbtvb8 PqtkB+1/D8DkbWANLh1hUs8SUnwIrXZ4q7GJbK9+jC4A5i2CVsHQJn0PAIzOVSbr 3AkumUYalMnAtk7AwJ0IJyuvHY2znqP+IcXLG2Y4GQ/vIpwKnHWK9jJVldYqTMxM q8sDFdeQ9/0bvw== =u1IL -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20181001-xtensa' into staging target/xtensa: preparation for FLIX support Separate generation of per-instruction code (such as raising exceptions and terminating TB) from per-opcode code. # gpg: Signature made Mon 01 Oct 2018 19:14:34 BST # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20181001-xtensa: target/xtensa: extract gen_check_interrupts call target/xtensa: make rsr/wsr helpers return void target/xtensa: extract unconditional TB termination via slot 0 target/xtensa: always end TB on CCOUNT access/CCOMPARE write target/xtensa: change SR number checks to assertions target/xtensa: extract unconditional TB termination target/xtensa: extract test for division by zero target/xtensa: extract test for cpdisabled exception target/xtensa: extract test for alloca exception target/xtensa: extract test for window underflow exception target/xtensa: extract test for window overflow exception target/xtensa: extract test for debug exception target/xtensa: extract test for syscall instruction target/xtensa: extract test for privileged instruction target/xtensa: extract test for an illegal instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
8f09da690f
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@ -217,6 +217,7 @@ enum {
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#define MEMCTL_IL0EN 0x1
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#define MAX_INSN_LENGTH 64
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#define MAX_INSN_SLOTS 32
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#define MAX_OPCODE_ARGS 16
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#define MAX_NAREG 64
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#define MAX_NINTERRUPT 32
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@ -347,11 +348,40 @@ typedef struct XtensaMemory {
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typedef struct DisasContext DisasContext;
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typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
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const uint32_t par[]);
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typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
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const uint32_t arg[],
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const uint32_t par[]);
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typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
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const uint32_t arg[],
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const uint32_t par[]);
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enum {
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XTENSA_OP_ILL = 0x1,
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XTENSA_OP_PRIVILEGED = 0x2,
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XTENSA_OP_SYSCALL = 0x4,
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XTENSA_OP_DEBUG_BREAK = 0x8,
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XTENSA_OP_OVERFLOW = 0x10,
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XTENSA_OP_UNDERFLOW = 0x20,
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XTENSA_OP_ALLOCA = 0x40,
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XTENSA_OP_COPROCESSOR = 0x80,
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XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
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XTENSA_OP_CHECK_INTERRUPTS = 0x200,
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XTENSA_OP_EXIT_TB_M1 = 0x400,
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XTENSA_OP_EXIT_TB_0 = 0x800,
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};
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typedef struct XtensaOpcodeOps {
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const char *name;
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XtensaOpcodeOp translate;
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XtensaOpcodeBoolTest test_ill;
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XtensaOpcodeUintTest test_overflow;
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const uint32_t *par;
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uint32_t op_flags;
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uint32_t windowed_register_op;
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uint32_t coprocessor;
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} XtensaOpcodeOps;
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typedef struct XtensaOpcodeTranslators {
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@ -661,6 +691,9 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
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#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
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#define XTENSA_TBFLAG_WINDOW_SHIFT 15
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#define XTENSA_TBFLAG_YIELD 0x20000
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#define XTENSA_TBFLAG_CWOE 0x40000
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#define XTENSA_TBFLAG_CALLINC_MASK 0x180000
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#define XTENSA_TBFLAG_CALLINC_SHIFT 19
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static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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@ -698,7 +731,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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(env->sregs[WINDOW_BASE] + 1);
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uint32_t w = ctz32(windowstart | 0x8);
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*flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
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*flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
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*flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
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PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
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} else {
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*flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
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}
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@ -57,12 +57,18 @@ static void init_libisa(XtensaConfig *config)
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{
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unsigned i, j;
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unsigned opcodes;
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unsigned formats;
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config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
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assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
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opcodes = xtensa_isa_num_opcodes(config->isa);
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formats = xtensa_isa_num_formats(config->isa);
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config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
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for (i = 0; i < formats; ++i) {
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assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS);
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}
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for (i = 0; i < opcodes; ++i) {
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const char *opc_name = xtensa_opcode_name(config->isa, i);
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XtensaOpcodeOps *ops = NULL;
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@ -5,6 +5,8 @@ DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
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DEF_HELPER_2(wsr_windowbase, void, env, i32)
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DEF_HELPER_4(entry, void, env, i32, i32, i32)
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DEF_HELPER_2(test_ill_retw, void, env, i32)
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DEF_HELPER_2(test_underflow_retw, void, env, i32)
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DEF_HELPER_2(retw, i32, env, i32)
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DEF_HELPER_2(rotw, void, env, i32)
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DEF_HELPER_3(window_check, noreturn, env, i32, i32)
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@ -253,22 +253,11 @@ void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
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void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
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{
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int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n",
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pc, env->sregs[PS]);
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HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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uint32_t windowstart = xtensa_replicate_windowstart(env) >>
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(env->sregs[WINDOW_BASE] + 1);
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if (windowstart & ((1 << callinc) - 1)) {
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HELPER(window_check)(env, pc, callinc);
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}
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env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
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xtensa_rotate_window(env, callinc);
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env->sregs[WINDOW_START] |=
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windowstart_bit(env->sregs[WINDOW_BASE], env);
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}
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env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
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xtensa_rotate_window(env, callinc);
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env->sregs[WINDOW_START] |=
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windowstart_bit(env->sregs[WINDOW_BASE], env);
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}
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void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
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}
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}
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uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
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void HELPER(test_ill_retw)(CPUXtensaState *env, uint32_t pc)
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{
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int n = (env->regs[0] >> 30) & 0x3;
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int m = 0;
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t windowstart = env->sregs[WINDOW_START];
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uint32_t ret_pc = 0;
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if (windowstart & windowstart_bit(windowbase - 1, env)) {
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m = 1;
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@ -314,35 +302,46 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
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m = 3;
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}
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if (n == 0 || (m != 0 && m != n) ||
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((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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if (n == 0 || (m != 0 && m != n)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
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"PS = %08x, m = %d, n = %d\n",
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pc, env->sregs[PS], m, n);
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HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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int owb = windowbase;
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}
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}
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ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
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void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc)
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{
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int n = (env->regs[0] >> 30) & 0x3;
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if (!(env->sregs[WINDOW_START] &
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windowstart_bit(env->sregs[WINDOW_BASE] - n, env))) {
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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xtensa_rotate_window(env, -n);
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if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
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env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
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} else {
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/* window underflow */
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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/* window underflow */
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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if (n == 1) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
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} else if (n == 2) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
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} else if (n == 3) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
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}
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if (n == 1) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
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} else if (n == 2) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
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} else if (n == 3) {
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HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
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}
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}
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}
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uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
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{
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int n = (env->regs[0] >> 30) & 0x3;
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
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xtensa_rotate_window(env, -n);
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env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env);
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return ret_pc;
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}
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