Enable PowerPC 64 MMU model and exceptions.
Cleanups in MMU exceptions generation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3319 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
0387d92875
commit
8f793433af
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@ -45,10 +45,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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if (rw == 2) {
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exception = POWERPC_EXCP_ISI;
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error_code = 0;
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error_code = 0x40000000;
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} else {
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exception = POWERPC_EXCP_DSI;
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error_code = 0;
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error_code = 0x40000000;
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if (rw)
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error_code |= 0x02000000;
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env->spr[SPR_DAR] = address;
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@ -1227,7 +1227,6 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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mmu_ctx_t ctx;
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int exception = 0, error_code = 0;
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int access_type;
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int ret = 0;
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@ -1253,40 +1252,34 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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cpu_dump_state(env, logfile, fprintf, 0);
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#endif
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if (access_type == ACCESS_CODE) {
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exception = POWERPC_EXCP_ISI;
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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switch (env->mmu_model) {
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case POWERPC_MMU_SOFT_6xx:
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exception = POWERPC_EXCP_IFTLB;
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env->exception_index = POWERPC_EXCP_IFTLB;
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env->error_code = 1 << 18;
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env->spr[SPR_IMISS] = address;
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env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
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error_code = 1 << 18;
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goto tlb_miss;
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case POWERPC_MMU_SOFT_74xx:
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exception = POWERPC_EXCP_IFTLB;
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env->exception_index = POWERPC_EXCP_IFTLB;
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goto tlb_miss_74xx;
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case POWERPC_MMU_SOFT_4xx:
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case POWERPC_MMU_SOFT_4xx_Z:
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exception = POWERPC_EXCP_ITLB;
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error_code = 0;
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env->exception_index = POWERPC_EXCP_ITLB;
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env->error_code = 0;
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env->spr[SPR_40x_DEAR] = address;
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env->spr[SPR_40x_ESR] = 0x00000000;
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break;
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case POWERPC_MMU_32B:
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error_code = 0x40000000;
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break;
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_64B:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case POWERPC_MMU_64BRIDGE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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#endif
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env->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x40000000;
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break;
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case POWERPC_MMU_601:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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@ -1310,64 +1303,65 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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break;
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case -2:
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/* Access rights violation */
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error_code = 0x08000000;
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env->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x08000000;
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break;
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case -3:
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/* No execute protection violation */
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error_code = 0x10000000;
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env->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x10000000;
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break;
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case -4:
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/* Direct store exception */
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/* No code fetch is allowed in direct-store areas */
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error_code = 0x10000000;
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env->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x10000000;
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break;
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#if defined(TARGET_PPC64)
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case -5:
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/* No match in segment table */
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exception = POWERPC_EXCP_ISEG;
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error_code = 0;
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env->exception_index = POWERPC_EXCP_ISEG;
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env->error_code = 0;
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break;
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#endif
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}
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} else {
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exception = POWERPC_EXCP_DSI;
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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switch (env->mmu_model) {
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case POWERPC_MMU_SOFT_6xx:
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if (rw == 1) {
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exception = POWERPC_EXCP_DSTLB;
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error_code = 1 << 16;
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env->exception_index = POWERPC_EXCP_DSTLB;
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env->error_code = 1 << 16;
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} else {
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exception = POWERPC_EXCP_DLTLB;
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error_code = 0;
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env->exception_index = POWERPC_EXCP_DLTLB;
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env->error_code = 0;
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}
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env->spr[SPR_DMISS] = address;
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env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
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tlb_miss:
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error_code |= ctx.key << 19;
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env->error_code |= ctx.key << 19;
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env->spr[SPR_HASH1] = ctx.pg_addr[0];
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env->spr[SPR_HASH2] = ctx.pg_addr[1];
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/* Do not alter DAR nor DSISR */
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goto out;
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break;
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case POWERPC_MMU_SOFT_74xx:
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if (rw == 1) {
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exception = POWERPC_EXCP_DSTLB;
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env->exception_index = POWERPC_EXCP_DSTLB;
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} else {
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exception = POWERPC_EXCP_DLTLB;
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env->exception_index = POWERPC_EXCP_DLTLB;
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}
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tlb_miss_74xx:
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/* Implement LRU algorithm */
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env->error_code = ctx.key << 19;
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env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
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((env->last_way + 1) & (env->nb_ways - 1));
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env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
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error_code = ctx.key << 19;
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break;
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case POWERPC_MMU_SOFT_4xx:
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case POWERPC_MMU_SOFT_4xx_Z:
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exception = POWERPC_EXCP_DTLB;
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error_code = 0;
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env->exception_index = POWERPC_EXCP_DTLB;
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env->error_code = 0;
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env->spr[SPR_40x_DEAR] = address;
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if (rw)
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env->spr[SPR_40x_ESR] = 0x00800000;
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@ -1375,18 +1369,18 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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env->spr[SPR_40x_ESR] = 0x00000000;
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break;
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case POWERPC_MMU_32B:
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error_code = 0x40000000;
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break;
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_64B:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case POWERPC_MMU_64BRIDGE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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#endif
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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if (rw == 1)
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env->spr[SPR_DSISR] = 0x42000000;
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else
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env->spr[SPR_DSISR] = 0x40000000;
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break;
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case POWERPC_MMU_601:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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@ -1410,52 +1404,66 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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break;
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case -2:
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/* Access rights violation */
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error_code = 0x08000000;
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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if (rw == 1)
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env->spr[SPR_DSISR] = 0x0A000000;
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else
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env->spr[SPR_DSISR] = 0x08000000;
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break;
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case -4:
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/* Direct store exception */
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switch (access_type) {
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case ACCESS_FLOAT:
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/* Floating point load/store */
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exception = POWERPC_EXCP_ALIGN;
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error_code = POWERPC_EXCP_ALIGN_FP;
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env->exception_index = POWERPC_EXCP_ALIGN;
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env->error_code = POWERPC_EXCP_ALIGN_FP;
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env->spr[SPR_DAR] = address;
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break;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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error_code = 0x04000000;
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/* lwarx, ldarx or stwcx. */
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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if (rw == 1)
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env->spr[SPR_DSISR] = 0x06000000;
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else
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env->spr[SPR_DSISR] = 0x04000000;
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break;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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error_code = 0x04100000;
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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if (rw == 1)
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env->spr[SPR_DSISR] = 0x06100000;
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else
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env->spr[SPR_DSISR] = 0x04100000;
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break;
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default:
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printf("DSI: invalid exception (%d)\n", ret);
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exception = POWERPC_EXCP_PROGRAM;
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error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
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env->exception_index = POWERPC_EXCP_PROGRAM;
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env->error_code =
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POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
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env->spr[SPR_DAR] = address;
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break;
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}
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break;
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#if defined(TARGET_PPC64)
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case -5:
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/* No match in segment table */
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exception = POWERPC_EXCP_DSEG;
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error_code = 0;
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env->exception_index = POWERPC_EXCP_DSEG;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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break;
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#endif
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}
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if (exception == POWERPC_EXCP_DSI && rw == 1)
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error_code |= 0x02000000;
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/* Store fault address */
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env->spr[SPR_DAR] = address;
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env->spr[SPR_DSISR] = error_code;
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}
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out:
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#if 0
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printf("%s: set exception to %d %02x\n",
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__func__, exception, error_code);
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printf("%s: set exception to %d %02x\n", __func__,
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env->exception, env->error_code);
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#endif
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env->exception_index = exception;
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env->error_code = error_code;
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ret = 1;
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}
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@ -2291,8 +2299,6 @@ static always_inline void powerpc_excp (CPUState *env,
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if (lpes1 == 0)
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msr_hv = 1;
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#endif
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/* XXX: TODO */
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cpu_abort(env, "Data segment exception is not implemented yet !\n");
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goto store_next;
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case POWERPC_EXCP_ISEG: /* Instruction segment exception */
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msr_ri = 0;
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@ -2300,9 +2306,6 @@ static always_inline void powerpc_excp (CPUState *env,
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if (lpes1 == 0)
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msr_hv = 1;
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#endif
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/* XXX: TODO */
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cpu_abort(env,
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"Instruction segment exception is not implemented yet !\n");
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goto store_next;
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#endif /* defined(TARGET_PPC64) */
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#if defined(TARGET_PPC64H)
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