target/mips: Decode microMIPS EVA load & store instructions
Implement decoding of microMIPS EVA load and store instruction groups in the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond() helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as opc. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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@ -12519,19 +12519,45 @@ enum {
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LWR = 0x1,
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SWR = 0x9,
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PREF = 0x2,
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/* 0xa is reserved */
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ST_EVA = 0xa,
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LL = 0x3,
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SC = 0xb,
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LDL = 0x4,
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SDL = 0xc,
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LDR = 0x5,
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SDR = 0xd,
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/* 0x6 is reserved */
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LD_EVA = 0x6,
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LWU = 0xe,
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LLD = 0x7,
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SCD = 0xf
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};
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/* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */
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enum {
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LBUE = 0x0,
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LHUE = 0x1,
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LWLE = 0x2,
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LWRE = 0x3,
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LBE = 0x4,
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LHE = 0x5,
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LLE = 0x6,
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LWE = 0x7,
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};
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/* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */
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enum {
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SWLE = 0x0,
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SWRE = 0x1,
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PREFE = 0x2,
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CACHEE = 0x3,
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SBE = 0x4,
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SHE = 0x5,
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SCE = 0x6,
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SWE = 0x7,
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};
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/* POOL32F encoding of minor opcode field (bits 5..0) */
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enum {
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@ -13832,7 +13858,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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uint16_t insn;
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int rt, rs, rd, rr;
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int16_t imm;
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uint32_t op, minor, mips32_op;
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uint32_t op, minor, minor2, mips32_op;
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uint32_t cond, fmt, cc;
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insn = cpu_lduw_code(env, ctx->pc + 2);
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@ -14777,7 +14803,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_ld(ctx, mips32_op, rt, rs, offset);
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break;
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do_st_lr:
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gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
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gen_st(ctx, mips32_op, rt, rs, offset);
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break;
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case SC:
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gen_st_cond(ctx, OPC_SC, rt, rs, offset);
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@ -14789,6 +14815,91 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
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break;
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#endif
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case LD_EVA:
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if (!ctx->eva) {
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MIPS_INVAL("pool32c ld-eva");
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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check_cp0_enabled(ctx);
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minor2 = (ctx->opcode >> 9) & 0x7;
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offset = sextract32(ctx->opcode, 0, 9);
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switch (minor2) {
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case LBUE:
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mips32_op = OPC_LBUE;
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goto do_ld_lr;
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case LHUE:
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mips32_op = OPC_LHUE;
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goto do_ld_lr;
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case LWLE:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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mips32_op = OPC_LWLE;
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goto do_ld_lr;
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case LWRE:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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mips32_op = OPC_LWRE;
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goto do_ld_lr;
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case LBE:
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mips32_op = OPC_LBE;
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goto do_ld_lr;
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case LHE:
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mips32_op = OPC_LHE;
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goto do_ld_lr;
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case LLE:
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mips32_op = OPC_LLE;
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goto do_ld_lr;
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case LWE:
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mips32_op = OPC_LWE;
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goto do_ld_lr;
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};
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break;
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case ST_EVA:
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if (!ctx->eva) {
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MIPS_INVAL("pool32c st-eva");
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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check_cp0_enabled(ctx);
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minor2 = (ctx->opcode >> 9) & 0x7;
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offset = sextract32(ctx->opcode, 0, 9);
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switch (minor2) {
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case SWLE:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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mips32_op = OPC_SWLE;
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goto do_st_lr;
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case SWRE:
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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mips32_op = OPC_SWRE;
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goto do_st_lr;
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case PREFE:
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/* Treat as no-op */
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if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
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/* hint codes 24-31 are reserved and signal RI */
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generate_exception(ctx, EXCP_RI);
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}
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break;
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case CACHEE:
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/* Treat as no-op */
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if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
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gen_cache_operation(ctx, rt, rs, offset);
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}
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break;
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case SBE:
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mips32_op = OPC_SBE;
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goto do_st_lr;
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case SHE:
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mips32_op = OPC_SHE;
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goto do_st_lr;
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case SCE:
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gen_st_cond(ctx, OPC_SCE, rt, rs, offset);
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break;
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case SWE:
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mips32_op = OPC_SWE;
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goto do_st_lr;
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};
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break;
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case PREF:
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/* Treat as no-op */
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if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
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