riscv: hart: Extract hart realize to a separate routine
Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -3,7 +3,7 @@
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Holds the state of a heterogenous array of RISC-V harts
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* Holds the state of a homogeneous array of RISC-V harts
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -39,26 +39,33 @@ static void riscv_harts_cpu_reset(void *opaque)
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cpu_reset(CPU(cpu));
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}
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static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
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char *cpu_type, Error **errp)
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{
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Error *err = NULL;
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
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sizeof(RISCVCPU), cpu_type,
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&error_abort, NULL);
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s->harts[idx].env.mhartid = idx;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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object_property_set_bool(OBJECT(&s->harts[idx]), true,
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"realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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static void riscv_harts_realize(DeviceState *dev, Error **errp)
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{
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RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
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Error *err = NULL;
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int n;
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s->harts = g_new0(RISCVCPU, s->num_harts);
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for (n = 0; n < s->num_harts; n++) {
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
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sizeof(RISCVCPU), s->cpu_type,
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&error_abort, NULL);
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s->harts[n].env.mhartid = n;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
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object_property_set_bool(OBJECT(&s->harts[n]), true,
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"realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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riscv_hart_realize(s, n, s->cpu_type, errp);
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}
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}
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