target/arm: Implement SCR_EL2.EEL2
This adds handling for the SCR_EL3.EEL2 bit. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com [PMM: Applied fixes for review issues noted by RTH: - check for FEATURE_AARCH64 before checking sel2 isar feature - correct the commit message subject line] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -480,7 +480,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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* masked from Secure state. The HCR and SCR settings
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* masked from Secure state. The HCR and SCR settings
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* don't affect the masking logic, only the interrupt routing.
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* don't affect the masking logic, only the interrupt routing.
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*/
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*/
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if (target_el == 3 || !secure) {
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if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
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unmasked = true;
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unmasked = true;
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}
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}
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} else {
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} else {
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@ -2164,7 +2164,10 @@ static inline bool arm_is_secure(CPUARMState *env)
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static inline bool arm_is_el2_enabled(CPUARMState *env)
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static inline bool arm_is_el2_enabled(CPUARMState *env)
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{
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{
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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return !arm_is_secure_below_el3(env);
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if (arm_is_secure_below_el3(env)) {
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return (env->cp15.scr_el3 & SCR_EEL2) != 0;
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}
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return true;
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}
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}
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return false;
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return false;
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}
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}
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@ -2211,7 +2214,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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return aa64;
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return aa64;
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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if (arm_feature(env, ARM_FEATURE_EL3) &&
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((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
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aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
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aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
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}
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}
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@ -533,6 +533,9 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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}
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}
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if (arm_is_secure_below_el3(env)) {
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if (arm_is_secure_below_el3(env)) {
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if (env->cp15.scr_el3 & SCR_EEL2) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_TRAP_EL3;
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return CP_ACCESS_TRAP_EL3;
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}
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}
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/* This will be EL1 NS and EL2 NS, which just UNDEF */
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/* This will be EL1 NS and EL2 NS, which just UNDEF */
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@ -2030,6 +2033,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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valid_mask |= SCR_API | SCR_APK;
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valid_mask |= SCR_API | SCR_APK;
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}
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}
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if (cpu_isar_feature(aa64_sel2, cpu)) {
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valid_mask |= SCR_EEL2;
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}
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if (cpu_isar_feature(aa64_mte, cpu)) {
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if (cpu_isar_feature(aa64_mte, cpu)) {
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valid_mask |= SCR_ATA;
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valid_mask |= SCR_ATA;
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}
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}
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@ -3388,13 +3394,16 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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bool isread)
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{
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{
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if (ri->opc2 & 4) {
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if (ri->opc2 & 4) {
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/* The ATS12NSO* operations must trap to EL3 if executed in
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/* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
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* Secure EL1 (which can only happen if EL3 is AArch64).
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* Secure EL1 (which can only happen if EL3 is AArch64).
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* They are simply UNDEF if executed from NS EL1.
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* They are simply UNDEF if executed from NS EL1.
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* They function normally from EL2 or EL3.
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* They function normally from EL2 or EL3.
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*/
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*/
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if (arm_current_el(env) == 1) {
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if (arm_current_el(env) == 1) {
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if (arm_is_secure_below_el3(env)) {
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if (arm_is_secure_below_el3(env)) {
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if (env->cp15.scr_el3 & SCR_EEL2) {
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return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
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}
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return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
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return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
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}
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}
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return CP_ACCESS_TRAP_UNCATEGORIZED;
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return CP_ACCESS_TRAP_UNCATEGORIZED;
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@ -3657,7 +3666,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
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static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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bool isread)
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{
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{
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if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
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if (arm_current_el(env) == 3 &&
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!(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
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return CP_ACCESS_TRAP;
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return CP_ACCESS_TRAP;
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}
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}
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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@ -5756,12 +5766,15 @@ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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bool isread)
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{
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{
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/* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
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/* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
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* At Secure EL1 it traps to EL3.
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* At Secure EL1 it traps to EL3 or EL2.
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*/
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*/
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if (arm_current_el(env) == 3) {
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if (arm_current_el(env) == 3) {
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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}
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}
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if (arm_is_secure_below_el3(env)) {
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if (arm_is_secure_below_el3(env)) {
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if (env->cp15.scr_el3 & SCR_EEL2) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_TRAP_EL3;
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return CP_ACCESS_TRAP_EL3;
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}
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}
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/* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
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/* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
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@ -2832,9 +2832,20 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
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}
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}
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if (s->current_el == 1) {
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if (s->current_el == 1) {
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/* If we're in Secure EL1 (which implies that EL3 is AArch64)
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/* If we're in Secure EL1 (which implies that EL3 is AArch64)
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* then accesses to Mon registers trap to EL3
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* then accesses to Mon registers trap to Secure EL2, if it exists,
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* otherwise EL3.
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*/
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*/
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TCGv_i32 tcg_el = tcg_const_i32(3);
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TCGv_i32 tcg_el;
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if (arm_dc_feature(s, ARM_FEATURE_AARCH64) &&
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dc_isar_feature(aa64_sel2, s)) {
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/* Target EL is EL<3 minus SCR_EL3.EEL2> */
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tcg_el = load_cpu_field(cp15.scr_el3);
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tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
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tcg_gen_addi_i32(tcg_el, tcg_el, 3);
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} else {
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tcg_el = tcg_const_i32(3);
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}
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gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
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gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
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tcg_temp_free_i32(tcg_el);
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tcg_temp_free_i32(tcg_el);
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