hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
In the SSE-300 the CPU_WAIT and NMI_ENABLE registers have moved offsets, so they are now where the SSE-200's WICCTRL and EWCTRL were. The SSE-300 does not have WICCTLR or EWCTRL at all, and the old offsets are reserved: Offset SSE-200 SSE-300 ----------------------------------- 0x118 CPUWAIT reserved 0x118 NMI_ENABLE reserved 0x120 WICCTRL CPUWAIT 0x124 EWCTRL NMI_ENABLE Handle this reshuffle, and the fact that SSE-300 has only one CPU and so only one active bit in CPUWAIT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-15-peter.maydell@linaro.org
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@ -172,7 +172,17 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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}
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}
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break;
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break;
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case A_CPUWAIT:
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case A_CPUWAIT:
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r = s->cpuwait;
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switch (s->sse_version) {
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case ARMSSE_IOTKIT:
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case ARMSSE_SSE200:
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r = s->cpuwait;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this is reserved (for INITSVTOR2) */
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goto bad_offset;
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default:
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g_assert_not_reached();
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}
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break;
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break;
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case A_NMI_ENABLE:
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case A_NMI_ENABLE:
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switch (s->sse_version) {
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switch (s->sse_version) {
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@ -183,12 +193,26 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_SSE200:
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case ARMSSE_SSE200:
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r = s->nmi_enable;
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r = s->nmi_enable;
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break;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this is reserved (for INITSVTOR3) */
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goto bad_offset;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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break;
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break;
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case A_WICCTRL:
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case A_WICCTRL:
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r = s->wicctrl;
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switch (s->sse_version) {
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case ARMSSE_IOTKIT:
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case ARMSSE_SSE200:
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r = s->wicctrl;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this offset is CPUWAIT */
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r = s->cpuwait;
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break;
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default:
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g_assert_not_reached();
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}
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break;
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break;
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case A_EWCTRL:
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case A_EWCTRL:
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switch (s->sse_version) {
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switch (s->sse_version) {
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@ -197,6 +221,10 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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case ARMSSE_SSE200:
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case ARMSSE_SSE200:
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r = s->ewctrl;
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r = s->ewctrl;
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break;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this offset is is NMI_ENABLE */
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r = s->nmi_enable;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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@ -279,6 +307,21 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
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return r;
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return r;
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}
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}
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static void cpuwait_write(IoTKitSysCtl *s, uint32_t value)
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{
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int num_cpus = (s->sse_version == ARMSSE_SSE300) ? 1 : 2;
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int i;
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for (i = 0; i < num_cpus; i++) {
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uint32_t mask = 1 << i;
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if ((s->cpuwait & mask) && !(value & mask)) {
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/* Powering up CPU 0 */
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arm_set_cpu_on_and_reset(i);
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}
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}
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s->cpuwait = value;
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}
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static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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@ -319,19 +362,32 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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set_init_vtor(0, s->initsvtor0);
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set_init_vtor(0, s->initsvtor0);
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break;
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break;
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case A_CPUWAIT:
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case A_CPUWAIT:
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if ((s->cpuwait & 1) && !(value & 1)) {
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switch (s->sse_version) {
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/* Powering up CPU 0 */
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case ARMSSE_IOTKIT:
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arm_set_cpu_on_and_reset(0);
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case ARMSSE_SSE200:
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cpuwait_write(s, value);
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this is reserved (for INITSVTOR2) */
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goto bad_offset;
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default:
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g_assert_not_reached();
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}
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}
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if ((s->cpuwait & 2) && !(value & 2)) {
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/* Powering up CPU 1 */
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arm_set_cpu_on_and_reset(1);
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}
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s->cpuwait = value;
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break;
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break;
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case A_WICCTRL:
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case A_WICCTRL:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
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switch (s->sse_version) {
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s->wicctrl = value;
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case ARMSSE_IOTKIT:
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case ARMSSE_SSE200:
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n");
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s->wicctrl = value;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this offset is CPUWAIT */
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cpuwait_write(s, value);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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break;
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case A_SECDBGSET:
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case A_SECDBGSET:
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/* write-1-to-set */
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/* write-1-to-set */
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@ -420,6 +476,11 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
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s->ewctrl = value;
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s->ewctrl = value;
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break;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this offset is is NMI_ENABLE */
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
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s->nmi_enable = value;
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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@ -499,6 +560,9 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
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qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
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s->nmi_enable = value;
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s->nmi_enable = value;
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break;
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break;
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case ARMSSE_SSE300:
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/* In SSE300 this is reserved (for INITSVTOR3) */
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goto bad_offset;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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