pc: acpi: isolate FADT specific data into AcpiFadtData structure
move FADT data initialization out of fadt_setup() into dedicated init_fadt_data() that will set common for pc/q35 values in AcpiFadtData structure and acpi_get_pm_info() will complement it with pc/q35 specific values initialization. That will allow to get rid of fadt_setup() and generalize build_fadt() so it could be easily extended for rev5 and reused by ARM target. While at it also move facs/dsdt/xdsdt offsets from build_fadt() arg list into AcpiFadtData, as they belong to the same dataset. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
f8eaef67a3
commit
937d1b5871
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@ -91,17 +91,11 @@ typedef struct AcpiMcfgInfo {
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} AcpiMcfgInfo;
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typedef struct AcpiPmInfo {
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bool force_rev1_fadt;
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bool s3_disabled;
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bool s4_disabled;
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bool pcihp_bridge_en;
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uint8_t s4_val;
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uint16_t sci_int;
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uint8_t acpi_enable_cmd;
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uint8_t acpi_disable_cmd;
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uint32_t gpe0_blk;
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uint32_t gpe0_blk_len;
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uint32_t io_base;
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AcpiFadtData fadt;
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uint16_t cpu_hp_io_base;
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uint16_t pcihp_io_base;
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uint16_t pcihp_io_len;
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@ -124,20 +118,59 @@ typedef struct AcpiBuildPciBusHotplugState {
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bool pcihp_bridge_en;
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} AcpiBuildPciBusHotplugState;
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static void init_common_fadt_data(Object *o, AcpiFadtData *data)
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{
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uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
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AmlAddressSpace as = AML_AS_SYSTEM_IO;
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AcpiFadtData fadt = {
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.rev = 3,
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.flags =
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(1 << ACPI_FADT_F_WBINVD) |
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(1 << ACPI_FADT_F_PROC_C1) |
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(1 << ACPI_FADT_F_SLP_BUTTON) |
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(1 << ACPI_FADT_F_RTC_S4) |
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(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
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/* APIC destination mode ("Flat Logical") has an upper limit of 8
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* CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
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* used
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*/
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((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
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.int_model = 1 /* Multiple APIC */,
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.rtc_century = RTC_CENTURY,
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.plvl2_lat = 0xfff /* C2 state not supported */,
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.plvl3_lat = 0xfff /* C3 state not supported */,
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.smi_cmd = ACPI_PORT_SMI_CMD,
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.sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
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.acpi_enable_cmd =
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object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
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.acpi_disable_cmd =
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object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
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.pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
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.pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
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.address = io + 0x04 },
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.pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
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.gpe0_blk = { .space_id = as, .bit_width =
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object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
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.address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
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},
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};
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*data = fadt;
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}
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static void acpi_get_pm_info(AcpiPmInfo *pm)
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{
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Object *piix = piix4_pm_find();
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Object *lpc = ich9_lpc_find();
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Object *obj = piix ? piix : lpc;
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QObject *o;
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pm->force_rev1_fadt = false;
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pm->cpu_hp_io_base = 0;
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pm->pcihp_io_base = 0;
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pm->pcihp_io_len = 0;
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init_common_fadt_data(obj, &pm->fadt);
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if (piix) {
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/* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
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pm->force_rev1_fadt = true;
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pm->fadt.rev = 1;
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pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
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pm->pcihp_io_base =
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object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
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@ -145,10 +178,19 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
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object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
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}
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if (lpc) {
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struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
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.bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
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pm->fadt.reset_reg = r;
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pm->fadt.reset_val = 0xf;
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pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
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pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
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}
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assert(obj);
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/* The above need not be conditional on machine type because the reset port
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* happens to be the same on PIIX (pc) and ICH9 (q35). */
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QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
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/* Fill in optional s3/s4 related properties */
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o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
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if (o) {
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@ -172,22 +214,6 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
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}
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qobject_decref(o);
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/* Fill in mandatory properties */
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pm->sci_int = object_property_get_uint(obj, ACPI_PM_PROP_SCI_INT, NULL);
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pm->acpi_enable_cmd = object_property_get_uint(obj,
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ACPI_PM_PROP_ACPI_ENABLE_CMD,
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NULL);
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pm->acpi_disable_cmd =
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object_property_get_uint(obj,
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ACPI_PM_PROP_ACPI_DISABLE_CMD,
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NULL);
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pm->io_base = object_property_get_uint(obj, ACPI_PM_PROP_PM_IO_BASE,
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NULL);
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pm->gpe0_blk = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK,
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NULL);
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pm->gpe0_blk_len = object_property_get_uint(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
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NULL);
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pm->pcihp_bridge_en =
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object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
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NULL);
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@ -273,73 +299,53 @@ build_facs(GArray *table_data, BIOSLinker *linker)
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}
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/* Load chipset information in FADT */
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static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm)
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static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiFadtData f)
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{
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fadt->model = 1;
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fadt->model = f.int_model;
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fadt->reserved1 = 0;
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fadt->sci_int = cpu_to_le16(pm->sci_int);
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fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
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fadt->acpi_enable = pm->acpi_enable_cmd;
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fadt->acpi_disable = pm->acpi_disable_cmd;
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fadt->sci_int = cpu_to_le16(f.sci_int);
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fadt->smi_cmd = cpu_to_le32(f.smi_cmd);
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fadt->acpi_enable = f.acpi_enable_cmd;
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fadt->acpi_disable = f.acpi_disable_cmd;
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/* EVT, CNT, TMR offset matches hw/acpi/core.c */
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fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
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fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
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fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
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fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
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fadt->pm1a_evt_blk = cpu_to_le32(f.pm1a_evt.address);
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fadt->pm1a_cnt_blk = cpu_to_le32(f.pm1a_cnt.address);
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fadt->pm_tmr_blk = cpu_to_le32(f.pm_tmr.address);
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fadt->gpe0_blk = cpu_to_le32(f.gpe0_blk.address);
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/* EVT, CNT, TMR length matches hw/acpi/core.c */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = pm->gpe0_blk_len;
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fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
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fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
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fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
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(1 << ACPI_FADT_F_PROC_C1) |
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(1 << ACPI_FADT_F_SLP_BUTTON) |
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(1 << ACPI_FADT_F_RTC_S4));
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fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
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/* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
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* For more than 8 CPUs, "Clustered Logical" mode has to be used
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*/
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if (max_cpus > 8) {
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fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
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}
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fadt->century = RTC_CENTURY;
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if (pm->force_rev1_fadt) {
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fadt->pm1_evt_len = f.pm1a_evt.bit_width / 8;
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fadt->pm1_cnt_len = f.pm1a_cnt.bit_width / 8;
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fadt->pm_tmr_len = f.pm_tmr.bit_width / 8;
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fadt->gpe0_blk_len = f.gpe0_blk.bit_width / 8;
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fadt->plvl2_lat = cpu_to_le16(f.plvl2_lat);
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fadt->plvl3_lat = cpu_to_le16(f.plvl3_lat);
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fadt->flags = cpu_to_le32(f.flags);
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fadt->century = f.rtc_century;
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if (f.rev == 1) {
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return;
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}
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fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP);
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fadt->reset_value = 0xf;
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fadt->reset_register.space_id = AML_SYSTEM_IO;
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fadt->reset_register.bit_width = 8;
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fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT);
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/* The above need not be conditional on machine type because the reset port
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* happens to be the same on PIIX (pc) and ICH9 (q35). */
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QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
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fadt->reset_value = f.reset_val;
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fadt->reset_register = f.reset_reg;
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fadt->reset_register.address = cpu_to_le64(f.reset_reg.address);
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fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO;
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fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8;
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fadt->xpm1a_event_block.address = cpu_to_le64(pm->io_base);
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fadt->xpm1a_event_block = f.pm1a_evt;
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fadt->xpm1a_event_block.address = cpu_to_le64(f.pm1a_evt.address);
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fadt->xpm1a_control_block.space_id = AML_SYSTEM_IO;
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fadt->xpm1a_control_block.bit_width = fadt->pm1_cnt_len * 8;
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fadt->xpm1a_control_block.address = cpu_to_le64(pm->io_base + 0x4);
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fadt->xpm1a_control_block = f.pm1a_cnt;
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fadt->xpm1a_control_block.address = cpu_to_le64(f.pm1a_cnt.address);
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fadt->xpm_timer_block.space_id = AML_SYSTEM_IO;
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fadt->xpm_timer_block.bit_width = fadt->pm_tmr_len * 8;
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fadt->xpm_timer_block.address = cpu_to_le64(pm->io_base + 0x8);
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fadt->xpm_timer_block = f.pm_tmr;
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fadt->xpm_timer_block.address = cpu_to_le64(f.pm_tmr.address);
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fadt->xgpe0_block.space_id = AML_SYSTEM_IO;
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fadt->xgpe0_block.bit_width = pm->gpe0_blk_len * 8;
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fadt->xgpe0_block.address = cpu_to_le64(pm->gpe0_blk);
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fadt->xgpe0_block = f.gpe0_blk;
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fadt->xgpe0_block.address = cpu_to_le64(f.gpe0_blk.address);
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}
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/* FADT */
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static void
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build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
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unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
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build_fadt(GArray *table_data, BIOSLinker *linker, AcpiFadtData *f,
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const char *oem_id, const char *oem_table_id)
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{
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AcpiFadtDescriptorRev3 *fadt = acpi_data_push(table_data, sizeof(*fadt));
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@ -347,29 +353,29 @@ build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
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unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
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unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data;
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int fadt_size = sizeof(*fadt);
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int rev = 3;
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/* FACS address to be filled by Guest linker */
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bios_linker_loader_add_pointer(linker,
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ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
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ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
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ACPI_BUILD_TABLE_FILE, *f->facs_tbl_offset);
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/* DSDT address to be filled by Guest linker */
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fadt_setup(fadt, pm);
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fadt_setup(fadt, *f);
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bios_linker_loader_add_pointer(linker,
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ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
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ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
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if (pm->force_rev1_fadt) {
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rev = 1;
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ACPI_BUILD_TABLE_FILE, *f->dsdt_tbl_offset);
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if (f->rev == 1) {
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fadt_size = offsetof(typeof(*fadt), reset_register);
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} else {
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} else if (f->xdsdt_tbl_offset) {
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bios_linker_loader_add_pointer(linker,
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ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt),
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ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
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ACPI_BUILD_TABLE_FILE, *f->xdsdt_tbl_offset);
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}
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build_header(linker, table_data,
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(void *)fadt, "FACP", fadt_size, rev, oem_id, oem_table_id);
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(void *)fadt, "FACP", fadt_size, f->rev,
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oem_id, oem_table_id);
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}
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void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
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@ -2049,7 +2055,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
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aml_io(
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AML_DECODE16,
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pm->fadt.gpe0_blk.address,
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pm->fadt.gpe0_blk.address,
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1,
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pm->fadt.gpe0_blk.bit_width / 8)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(scope, dev);
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@ -2696,7 +2707,10 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
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/* ACPI tables pointed to by RSDT */
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fadt = tables_blob->len;
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acpi_add_table(table_offsets, tables_blob);
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build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
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pm.fadt.facs_tbl_offset = &facs;
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pm.fadt.dsdt_tbl_offset = &dsdt;
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pm.fadt.xdsdt_tbl_offset = &dsdt;
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build_fadt(tables_blob, tables->linker, &pm.fadt,
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slic_oem.id, slic_oem.table_id);
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aml_len += tables_blob->len - fadt;
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@ -175,6 +175,34 @@ struct AcpiFadtDescriptorRev5_1 {
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typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
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typedef struct AcpiFadtData {
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struct AcpiGenericAddress pm1a_cnt; /* PM1a_CNT_BLK */
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struct AcpiGenericAddress pm1a_evt; /* PM1a_EVT_BLK */
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struct AcpiGenericAddress pm_tmr; /* PM_TMR_BLK */
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struct AcpiGenericAddress gpe0_blk; /* GPE0_BLK */
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struct AcpiGenericAddress reset_reg; /* RESET_REG */
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uint8_t reset_val; /* RESET_VALUE */
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uint8_t rev; /* Revision */
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uint32_t flags; /* Flags */
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uint32_t smi_cmd; /* SMI_CMD */
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uint16_t sci_int; /* SCI_INT */
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uint8_t int_model; /* INT_MODEL */
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uint8_t acpi_enable_cmd; /* ACPI_ENABLE */
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uint8_t acpi_disable_cmd; /* ACPI_DISABLE */
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uint8_t rtc_century; /* CENTURY */
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uint16_t plvl2_lat; /* P_LVL2_LAT */
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uint16_t plvl3_lat; /* P_LVL3_LAT */
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/*
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* respective tables offsets within ACPI_BUILD_TABLE_FILE,
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* NULL if table doesn't exist (in that case field's value
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* won't be patched by linker and will be kept set to 0)
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*/
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unsigned *facs_tbl_offset; /* FACS offset in */
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unsigned *dsdt_tbl_offset;
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unsigned *xdsdt_tbl_offset;
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} AcpiFadtData;
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#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
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#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
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||||
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||||
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Loading…
Reference in a new issue