target/i386: move cpu_cc_srcT to DisasContext
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -73,7 +73,7 @@
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/* global register indexes */
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static TCGv cpu_A0;
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static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
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static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2;
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static TCGv_i32 cpu_cc_op;
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static TCGv cpu_regs[CPU_NB_REGS];
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static TCGv cpu_seg_base[6];
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@ -135,6 +135,10 @@ typedef struct DisasContext {
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int cpuid_ext3_features;
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int cpuid_7_0_ebx_features;
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int cpuid_xsave_features;
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/* TCG local temps */
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TCGv cc_srcT;
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sigjmp_buf jmpbuf;
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} DisasContext;
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@ -244,7 +248,7 @@ static void set_cc_op(DisasContext *s, CCOp op)
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tcg_gen_discard_tl(cpu_cc_src2);
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}
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if (dead & USES_CC_SRCT) {
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tcg_gen_discard_tl(cpu_cc_srcT);
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tcg_gen_discard_tl(s->cc_srcT);
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}
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if (op == CC_OP_DYNAMIC) {
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@ -667,11 +671,11 @@ static inline void gen_op_testl_T0_T1_cc(void)
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tcg_gen_and_tl(cpu_cc_dst, cpu_T0, cpu_T1);
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}
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static void gen_op_update_neg_cc(void)
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static void gen_op_update_neg_cc(DisasContext *s)
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{
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
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tcg_gen_neg_tl(cpu_cc_src, cpu_T0);
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tcg_gen_movi_tl(cpu_cc_srcT, 0);
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tcg_gen_movi_tl(s->cc_srcT, 0);
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}
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/* compute all eflags to cc_src */
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@ -742,7 +746,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
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t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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/* If no temporary was used, be careful not to alias t1 and t0. */
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t0 = t1 == cpu_cc_src ? cpu_tmp0 : reg;
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tcg_gen_mov_tl(t0, cpu_cc_srcT);
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tcg_gen_mov_tl(t0, s->cc_srcT);
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gen_extu(size, t0);
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goto add_sub;
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@ -899,7 +903,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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size = s->cc_op - CC_OP_SUBB;
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switch (jcc_op) {
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case JCC_BE:
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tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT);
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tcg_gen_mov_tl(cpu_tmp4, s->cc_srcT);
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gen_extu(size, cpu_tmp4);
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t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4,
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@ -912,7 +916,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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case JCC_LE:
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cond = TCG_COND_LE;
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fast_jcc_l:
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tcg_gen_mov_tl(cpu_tmp4, cpu_cc_srcT);
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tcg_gen_mov_tl(cpu_tmp4, s->cc_srcT);
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gen_exts(size, cpu_tmp4);
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t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true);
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cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4,
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@ -1309,11 +1313,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
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case OP_SUBL:
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if (s1->prefix & PREFIX_LOCK) {
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tcg_gen_neg_tl(cpu_T0, cpu_T1);
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tcg_gen_atomic_fetch_add_tl(cpu_cc_srcT, cpu_A0, cpu_T0,
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tcg_gen_atomic_fetch_add_tl(s1->cc_srcT, cpu_A0, cpu_T0,
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s1->mem_index, ot | MO_LE);
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tcg_gen_sub_tl(cpu_T0, cpu_cc_srcT, cpu_T1);
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tcg_gen_sub_tl(cpu_T0, s1->cc_srcT, cpu_T1);
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} else {
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tcg_gen_mov_tl(cpu_cc_srcT, cpu_T0);
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tcg_gen_mov_tl(s1->cc_srcT, cpu_T0);
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tcg_gen_sub_tl(cpu_T0, cpu_T0, cpu_T1);
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gen_op_st_rm_T0_A0(s1, ot, d);
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}
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@ -1356,7 +1360,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
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break;
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case OP_CMPL:
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tcg_gen_mov_tl(cpu_cc_src, cpu_T1);
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tcg_gen_mov_tl(cpu_cc_srcT, cpu_T0);
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tcg_gen_mov_tl(s1->cc_srcT, cpu_T0);
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tcg_gen_sub_tl(cpu_cc_dst, cpu_T0, cpu_T1);
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set_cc_op(s1, CC_OP_SUBB + ot);
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break;
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@ -4823,7 +4827,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_op_mov_reg_v(ot, rm, cpu_T0);
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}
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}
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gen_op_update_neg_cc();
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gen_op_update_neg_cc(s);
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set_cc_op(s, CC_OP_SUBB + ot);
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break;
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case 4: /* mul */
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@ -5283,7 +5287,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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}
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tcg_gen_mov_tl(cpu_cc_src, oldv);
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tcg_gen_mov_tl(cpu_cc_srcT, cmpv);
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tcg_gen_mov_tl(s->cc_srcT, cmpv);
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tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
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set_cc_op(s, CC_OP_SUBB + ot);
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tcg_temp_free(oldv);
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@ -8463,7 +8467,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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cpu_tmp4 = tcg_temp_new();
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cpu_ptr0 = tcg_temp_new_ptr();
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cpu_ptr1 = tcg_temp_new_ptr();
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cpu_cc_srcT = tcg_temp_local_new();
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dc->cc_srcT = tcg_temp_local_new();
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}
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static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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