target-mips: make sure constants are in the second argument
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
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cc739bb0c4
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@ -803,9 +803,9 @@ generate_exception (DisasContext *ctx, int excp)
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}
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}
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/* Addresses computation */
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/* Addresses computation */
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static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
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static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
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{
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{
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tcg_gen_add_tl(t0, t0, t1);
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tcg_gen_add_tl(ret, arg0, arg1);
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#if defined(TARGET_MIPS64)
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#if defined(TARGET_MIPS64)
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/* For compatibility with 32-bit code, data reference in user mode
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/* For compatibility with 32-bit code, data reference in user mode
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@ -813,7 +813,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
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See the MIPS64 PRA manual, section 4.10. */
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See the MIPS64 PRA manual, section 4.10. */
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if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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!(ctx->hflags & MIPS_HFLAG_UX)) {
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!(ctx->hflags & MIPS_HFLAG_UX)) {
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tcg_gen_ext32s_i64(t0, t0);
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tcg_gen_ext32s_i64(ret, ret);
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}
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}
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#endif
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#endif
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}
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}
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@ -1005,7 +1005,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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gen_load_gpr(t0, base);
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gen_load_gpr(t0, base);
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} else {
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} else {
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tcg_gen_movi_tl(t0, offset);
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tcg_gen_movi_tl(t0, offset);
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gen_op_addr_add(ctx, t0, cpu_gpr[base]);
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gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
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}
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}
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/* Don't do NOP if destination is zero: we must perform the actual
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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memory access. */
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@ -1163,7 +1163,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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gen_load_gpr(t0, base);
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gen_load_gpr(t0, base);
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} else {
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} else {
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tcg_gen_movi_tl(t0, offset);
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tcg_gen_movi_tl(t0, offset);
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gen_op_addr_add(ctx, t0, cpu_gpr[base]);
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gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
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}
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}
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/* Don't do NOP if destination is zero: we must perform the actual
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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memory access. */
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@ -1202,7 +1202,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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gen_load_gpr(t0, base);
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gen_load_gpr(t0, base);
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} else {
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} else {
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tcg_gen_movi_tl(t0, offset);
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tcg_gen_movi_tl(t0, offset);
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gen_op_addr_add(ctx, t0, cpu_gpr[base]);
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gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
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}
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}
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/* Don't do NOP if destination is zero: we must perform the actual
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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memory access. */
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@ -7264,7 +7264,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
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gen_load_gpr(t0, base);
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gen_load_gpr(t0, base);
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} else {
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} else {
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gen_load_gpr(t0, index);
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gen_load_gpr(t0, index);
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gen_op_addr_add(ctx, t0, cpu_gpr[base]);
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gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
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}
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}
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/* Don't do NOP if destination is zero: we must perform the actual
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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memory access. */
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