target-ppc: Return page shift from PTEG search
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it didn't previously do. This means we're now double decoding the page size because we check it int he fault path after ppc64_hash64_htab_lookup() returns. To avoid this duplication have ppc_hash64_pteg_search() and ppc_hash64_htab_lookup() return the page size from the PTE and use that in the callers instead of decoding again. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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073de86aa9
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@ -489,7 +489,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
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static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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ppc_slb_t *slb, target_ulong ptem,
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ppc_slb_t *slb, target_ulong ptem,
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ppc_hash_pte64_t *pte)
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ppc_hash_pte64_t *pte, unsigned *pshift)
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{
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{
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CPUPPCState *env = &cpu->env;
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CPUPPCState *env = &cpu->env;
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int i;
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int i;
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@ -508,7 +508,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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/* This compares V, B, H (secondary) and the AVPN */
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/* This compares V, B, H (secondary) and the AVPN */
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if (HPTE64_V_COMPARE(pte0, ptem)) {
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if (HPTE64_V_COMPARE(pte0, ptem)) {
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unsigned pshift = hpte_page_shift(slb->sps, pte0, pte1);
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*pshift = hpte_page_shift(slb->sps, pte0, pte1);
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/*
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/*
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* If there is no match, ignore the PTE, it could simply
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* If there is no match, ignore the PTE, it could simply
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* be for a different segment size encoding and the
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* be for a different segment size encoding and the
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@ -516,7 +516,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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* potentially leave behind PTEs for the wrong base page
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* potentially leave behind PTEs for the wrong base page
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* size when demoting segments.
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* size when demoting segments.
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*/
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*/
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if (pshift == 0) {
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if (*pshift == 0) {
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continue;
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continue;
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}
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}
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/* We don't do anything with pshift yet as qemu TLB only deals
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/* We don't do anything with pshift yet as qemu TLB only deals
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@ -537,7 +537,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
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static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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ppc_slb_t *slb, target_ulong eaddr,
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ppc_slb_t *slb, target_ulong eaddr,
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ppc_hash_pte64_t *pte)
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ppc_hash_pte64_t *pte, unsigned *pshift)
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{
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{
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CPUPPCState *env = &cpu->env;
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CPUPPCState *env = &cpu->env;
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hwaddr pte_offset;
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hwaddr pte_offset;
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@ -576,7 +576,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte);
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pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte, pshift);
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if (pte_offset == -1) {
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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/* Secondary PTEG lookup */
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@ -587,7 +587,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ptem, ~hash);
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env->htab_mask, vsid, ptem, ~hash);
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pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte);
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pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte, pshift);
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}
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}
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return pte_offset;
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return pte_offset;
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@ -714,7 +714,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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}
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}
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/* 4. Locate the PTE in the hash table */
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/* 4. Locate the PTE in the hash table */
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
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if (pte_offset == -1) {
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if (pte_offset == -1) {
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dsisr = 0x40000000;
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dsisr = 0x40000000;
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if (rwx == 2) {
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if (rwx == 2) {
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@ -730,18 +730,6 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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qemu_log_mask(CPU_LOG_MMU,
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qemu_log_mask(CPU_LOG_MMU,
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"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* Validate page size encoding */
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apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
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if (!apshift) {
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error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
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" @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
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/* Not entirely sure what the right action here, but machine
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* check seems reasonable */
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cs->exception_index = POWERPC_EXCP_MCHECK;
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env->error_code = 0;
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return 1;
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}
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/* 5. Check access permissions */
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/* 5. Check access permissions */
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pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
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pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
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@ -815,16 +803,11 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
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return -1;
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return -1;
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}
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}
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
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pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
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if (pte_offset == -1) {
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if (pte_offset == -1) {
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return -1;
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return -1;
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}
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}
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apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
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if (!apshift) {
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return -1;
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}
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return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
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return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
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& TARGET_PAGE_MASK;
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& TARGET_PAGE_MASK;
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}
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}
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