ppc patch queue for 2017-03-14
This set has a handful og bugfixes to go into qemu-2.9. This includes an update to the dtc/libfdt submodule which will fix the build errors seen on some distributions. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJYx2rpAAoJEGw4ysog2bOSKPYQANSrQFWEix7RRWqkoWfKim+B 8ZgLf9kPwn2ywjmAarymY/MHrnj5DsD8vOxWb8y81PX+j0RsJDt3h/GgDVhibvUE CKRnnkWQdvqaZO30CQqhthFn63NYA0WSyEOR7JUq4VaEftk6hkffptdcIoGixyk9 bFhXpSMyUeXtJW8RHxcCcgatqqQ7n6BX8fabw+QMPIvfU451hCdpzEgoAfTiXvOr jj2ShUu+Bz6hWQmGoE2Jkjqm/rfEcuQgO948TC64m153Rdd+WU9J07N4TYag0xRv GMR6leLvKJk+L5gWDjlPaUCQThLlEgo2XyME3dWRvUxUKyetKtJnsoQQ+WFd9Y8L wWbZGUQap6nGU19bwXkkPF5QlJwbAK3+QxwdiCot/aWfJxLmCsvtj57m7nUjq85y nyMch/48k6zvXZHSn1fXyRsiNrfkwUbdphuetAkgjoQKdjgDvb/xhCd9p2/73DFS acFyLBifNWvya9S+46OZVgqfGH7qSb3TQofTjaAHtNVEqY0m72PXLUtowSMQ61z0 ZPL2WIcA9cUtYcp0qGbDpZAkoYoC02nenbZTJ0/7sZ/kO0FoS8MxjfSKGqWePC8Q GXfi1m5RvM4o+wsJYQ99rK7siaKGOk3tmlN0uYWzzC+GF9h01YEAAbXjzWpF3s6y pqMhCvNBHUT2arz6k6R0 =dxrH -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging ppc patch queue for 2017-03-14 This set has a handful og bugfixes to go into qemu-2.9. This includes an update to the dtc/libfdt submodule which will fix the build errors seen on some distributions. # gpg: Signature made Tue 14 Mar 2017 04:00:41 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.9-20170314: dtc: Update submodule to avoid build errors pseries: Don't expose PCIe extended config space on older machine types target/ppc: fix cpu_ov setting for 32-bit target/ppc: Fix wrong number of UAMR register Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
94b5d57d2f
2
dtc
2
dtc
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@ -1 +1 @@
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Subproject commit fa8bc7f928ac25f23532afc8beb2073efc8fb063
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Subproject commit 558cd81bdd432769b59bff01240c44f82cfb1a9d
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@ -3163,8 +3163,13 @@ DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
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/*
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/*
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* pseries-2.8
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* pseries-2.8
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*/
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*/
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#define SPAPR_COMPAT_2_8 \
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#define SPAPR_COMPAT_2_8 \
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HW_COMPAT_2_8
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HW_COMPAT_2_8 \
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{ \
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.driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
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.property = "pcie-extended-configuration-space", \
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.value = "off", \
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},
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static void spapr_machine_2_8_instance_options(MachineState *machine)
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static void spapr_machine_2_8_instance_options(MachineState *machine)
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{
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{
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@ -1321,7 +1321,7 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
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_FDT(fdt_setprop(fdt, offset, "assigned-addresses",
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_FDT(fdt_setprop(fdt, offset, "assigned-addresses",
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(uint8_t *)rp.assigned, rp.assigned_len));
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(uint8_t *)rp.assigned, rp.assigned_len));
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if (pci_is_express(dev)) {
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if (sphb->pcie_ecs && pci_is_express(dev)) {
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_FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
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_FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
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}
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}
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@ -1858,6 +1858,8 @@ static Property spapr_phb_properties[] = {
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DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
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DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
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DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
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DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
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pre_2_8_migration, false),
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pre_2_8_migration, false),
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DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
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pcie_ecs, true),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -80,6 +80,8 @@ struct sPAPRPHBState {
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uint32_t numa_node;
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uint32_t numa_node;
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bool pcie_ecs; /* Allow access to PCIe extended config space? */
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/* Fields for migration compatibility hacks */
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/* Fields for migration compatibility hacks */
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bool pre_2_8_migration;
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bool pre_2_8_migration;
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uint32_t mig_liobn;
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uint32_t mig_liobn;
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@ -1408,7 +1408,7 @@ int ppc_compat_max_threads(PowerPCCPU *cpu);
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#define SPR_601_UDECR (0x006)
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#define SPR_601_UDECR (0x006)
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#define SPR_LR (0x008)
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#define SPR_LR (0x008)
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#define SPR_CTR (0x009)
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#define SPR_CTR (0x009)
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#define SPR_UAMR (0x00C)
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#define SPR_UAMR (0x00D)
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#define SPR_DSCR (0x011)
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#define SPR_DSCR (0x011)
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#define SPR_DSISR (0x012)
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#define SPR_DSISR (0x012)
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#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
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#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
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@ -818,7 +818,7 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
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if (is_isa300(ctx)) {
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if (is_isa300(ctx)) {
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tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
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tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
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}
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}
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tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
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tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
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}
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}
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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}
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}
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