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sun4m: move DMA device wiring from sparc32_dma_init() to sun4m_hw_init()

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By using the sysbus interface it is possible to wire up the esp/le devices
to the sun4m DMA controller directly during sun4m_hw_init() instead of
passing qemu_irqs into the sparc32_dma_init() function.

This is an intermediate step to allow further reorganisation as more logic
is moved into the relevant SPARC32 DMA devices; there will be a final
refactoring of sparc32_dma_init() once this work is complete.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland 2017-10-14 13:22:21 +01:00
parent 9db2cf3f29
commit 9540619d82
1 changed files with 16 additions and 13 deletions
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29
hw/sparc/sun4m.c
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@ -306,8 +306,7 @@ static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
return s;
}
static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, int is_ledma)
static void *sparc32_dma_init(hwaddr daddr, void *iommu, int is_ledma)
{
DeviceState *dev;
SysBusDevice *s;
@ -316,8 +315,6 @@ static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(s, 0, parent_irq);
*dev_irq = qdev_get_gpio_in(dev, 0);
sysbus_mmio_map(s, 0, daddr);
return s;
@ -819,9 +816,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
{
DeviceState *slavio_intctl;
unsigned int i;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
void *iommu, *nvram;
DeviceState *espdma, *ledma;
SysBusDevice *sbd;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
qemu_irq esp_reset, dma_enable;
qemu_irq fdc_tc;
unsigned long kernel_size;
@ -877,11 +875,13 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
}
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
iommu, &espdma_irq, 0);
espdma = sparc32_dma_init(hwdef->dma_base, iommu, 0);
sbd = SYS_BUS_DEVICE(espdma);
sysbus_connect_irq(sbd, 0, slavio_irq[18]);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[16], iommu, &ledma_irq, 1);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, iommu, 1);
sbd = SYS_BUS_DEVICE(ledma);
sysbus_connect_irq(sbd, 0, slavio_irq[16]);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
@ -934,7 +934,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
empty_slot_init(hwdef->sx_base, 0x2000);
}
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
lance_init(&nd_table[0], hwdef->le_base, ledma,
qdev_get_gpio_in(ledma, 0));
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
@ -966,7 +967,9 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, &esp_reset, &dma_enable);
espdma,
qdev_get_gpio_in(espdma, 0),
&esp_reset, &dma_enable);
qdev_connect_gpio_out(espdma, 0, esp_reset);
qdev_connect_gpio_out(espdma, 1, dma_enable);