haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Add statics and missing #includes for prototypes.

Browse source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3683 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2007-11-18 01:44:38 +00:00
parent 4c1b1bfe30
commit 9596ebb701
48 changed files with 137 additions and 145 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
audio/audio.c
View file

@ -238,7 +238,7 @@ static char *audio_alloc_prefix (const char *s)
return r;
}
const char *audio_audfmt_to_string (audfmt_e fmt)
static const char *audio_audfmt_to_string (audfmt_e fmt)
{
switch (fmt) {
case AUD_FMT_U8:
@ -264,7 +264,8 @@ const char *audio_audfmt_to_string (audfmt_e fmt)
return "S16";
}
audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval, int *defaultp)
static audfmt_e audio_string_to_audfmt (const char *s, audfmt_e defval,
int *defaultp)
{
if (!strcasecmp (s, "u8")) {
*defaultp = 0;

6
block-vvfat.c
View file

@ -175,7 +175,7 @@ static inline int array_roll(array_t* array,int index_to,int index_from,int coun
return 0;
}
inline int array_remove_slice(array_t* array,int index, int count)
static inline int array_remove_slice(array_t* array,int index, int count)
{
assert(index >=0);
assert(count > 0);
@ -186,13 +186,13 @@ inline int array_remove_slice(array_t* array,int index, int count)
return 0;
}
int array_remove(array_t* array,int index)
static int array_remove(array_t* array,int index)
{
return array_remove_slice(array, index, 1);
}
/* return the index for a given member */
int array_index(array_t* array, void* pointer)
static int array_index(array_t* array, void* pointer)
{
size_t offset = (char*)pointer - array->pointer;
assert(offset >= 0);

2
block.c
View file

@ -124,7 +124,7 @@ void path_combine(char *dest, int dest_size,
}
void bdrv_register(BlockDriver *bdrv)
static void bdrv_register(BlockDriver *bdrv)
{
if (!bdrv->bdrv_aio_read) {
/* add AIO emulation layer */

4
console.c
View file

@ -61,7 +61,7 @@ typedef struct QEMUFIFO {
int count, wptr, rptr;
} QEMUFIFO;
int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
static int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
{
int l, len;
@ -84,7 +84,7 @@ int qemu_fifo_write(QEMUFIFO *f, const uint8_t *buf, int len1)
return len1;
}
int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
static int qemu_fifo_read(QEMUFIFO *f, uint8_t *buf, int len1)
{
int l, len;

4
dyngen.c
View file

@ -232,7 +232,7 @@ enum {
int do_swap;
void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
static void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
@ -243,7 +243,7 @@ void __attribute__((noreturn)) __attribute__((format (printf, 1, 2))) error(cons
exit(1);
}
void *load_data(int fd, long offset, unsigned int size)
static void *load_data(int fd, long offset, unsigned int size)
{
char *data;

6
elf_ops.h
View file

@ -138,9 +138,9 @@ static int glue(load_symbols, SZ)(struct elfhdr *ehdr, int fd, int must_swab)
return -1;
}
int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
int must_swab, uint64_t *pentry,
uint64_t *lowaddr, uint64_t *highaddr)
static int glue(load_elf, SZ)(int fd, int64_t virt_to_phys_addend,
int must_swab, uint64_t *pentry,
uint64_t *lowaddr, uint64_t *highaddr)
{
struct elfhdr ehdr;
struct elf_phdr *phdr = NULL, *ph;

2
hw/arm_sysctl.c
View file

@ -8,7 +8,7 @@
*/
#include "hw.h"
#include "arm-misc.h"
#include "primecell.h"
#include "sysemu.h"
#define LOCK_VALUE 0xa05f

4
hw/arm_timer.c
View file

@ -8,8 +8,8 @@
*/
#include "hw.h"
#include "arm-misc.h"
#include "qemu-timer.h"
#include "primecell.h"
/* Common timer implementation. */
@ -43,7 +43,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;

2
hw/gt64xxx.c
View file

@ -908,7 +908,7 @@ static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
}
void gt64120_reset(void *opaque)
static void gt64120_reset(void *opaque)
{
GT64120State *s = opaque;

2
hw/i8259.c
View file

@ -178,7 +178,7 @@ void pic_update_irq(PicState2 *s)
int64_t irq_time[16];
#endif
void i8259_set_irq(void *opaque, int irq, int level)
static void i8259_set_irq(void *opaque, int irq, int level)
{
PicState2 *s = opaque;

1
hw/ide.c
View file

@ -30,6 +30,7 @@
#include "block.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "ppc_mac.h"
/* debug IDE devices */
//#define DEBUG_IDE

20
hw/mc146818rtc.c
View file

@ -390,7 +390,7 @@ void rtc_set_date(RTCState *s, const struct tm *tm)
#define REG_IBM_CENTURY_BYTE 0x32
#define REG_IBM_PS2_CENTURY_BYTE 0x37
void rtc_set_date_from_host(RTCState *s)
static void rtc_set_date_from_host(RTCState *s)
{
time_t ti;
struct tm *tm;
@ -498,22 +498,22 @@ RTCState *rtc_init(int base, qemu_irq irq)
}
/* Memory mapped interface */
uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}
void cmos_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void cmos_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}
uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@ -525,8 +525,8 @@ uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
return val;
}
void cmos_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void cmos_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -535,7 +535,7 @@ void cmos_mm_writew (void *opaque,
cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}
uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@ -547,8 +547,8 @@ uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
return val;
}
void cmos_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void cmos_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN

2
hw/mcf_fec.c
View file

@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
}
}
void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {

4
hw/mips_malta.c
View file

@ -398,7 +398,7 @@ static CPUWriteMemoryFunc *malta_fpga_write[] = {
malta_fpga_writel
};
void malta_fpga_reset(void *opaque)
static void malta_fpga_reset(void *opaque)
{
MaltaFPGAState *s = opaque;
@ -415,7 +415,7 @@ void malta_fpga_reset(void *opaque)
malta_fpga_update_display(s);
}
MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
{
MaltaFPGAState *s;
CharDriverState *uart_chr;

1
hw/ne2000.c
View file

@ -23,6 +23,7 @@
*/
#include "hw.h"
#include "pci.h"
#include "pc.h"
#include "net.h"
/* debug NE2000 card */

1
hw/nvram.h
View file

@ -37,5 +37,6 @@ void m48t59_toggle_lock (void *private, int lock);
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
uint32_t io_base, uint16_t size,
int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
#endif /* !NVRAM_H */

18
hw/omap.c
View file

@ -3041,7 +3041,7 @@ static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
omap_badwidth_write16,
};
void omap_mpuio_reset(struct omap_mpuio_s *s)
static void omap_mpuio_reset(struct omap_mpuio_s *s)
{
s->inputs = 0;
s->outputs = 0;
@ -3257,7 +3257,7 @@ static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
omap_badwidth_write16,
};
void omap_gpio_reset(struct omap_gpio_s *s)
static void omap_gpio_reset(struct omap_gpio_s *s)
{
s->inputs = 0;
s->outputs = ~0;
@ -3429,7 +3429,7 @@ static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
omap_badwidth_write16,
};
void omap_uwire_reset(struct omap_uwire_s *s)
static void omap_uwire_reset(struct omap_uwire_s *s)
{
s->control = 0;
s->setup[0] = 0;
@ -3470,7 +3470,7 @@ void omap_uwire_attach(struct omap_uwire_s *s,
}
/* Pseudonoise Pulse-Width Light Modulator */
void omap_pwl_update(struct omap_mpu_state_s *s)
static void omap_pwl_update(struct omap_mpu_state_s *s)
{
int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
@ -3528,7 +3528,7 @@ static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
omap_badwidth_write8,
};
void omap_pwl_reset(struct omap_mpu_state_s *s)
static void omap_pwl_reset(struct omap_mpu_state_s *s)
{
s->pwl.output = 0;
s->pwl.level = 0;
@ -3632,7 +3632,7 @@ static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
omap_badwidth_write8,
};
void omap_pwt_reset(struct omap_mpu_state_s *s)
static void omap_pwt_reset(struct omap_mpu_state_s *s)
{
s->pwt.frc = 0;
s->pwt.vrc = 0;
@ -4037,7 +4037,7 @@ static void omap_rtc_tick(void *opaque)
qemu_mod_timer(s->clk, s->tick);
}
void omap_rtc_reset(struct omap_rtc_s *s)
static void omap_rtc_reset(struct omap_rtc_s *s)
{
s->interrupts = 0;
s->comp_reg = 0;
@ -4509,14 +4509,14 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
return s;
}
void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
omap_mcbsp_rx_start(s);
}
void omap_mcbsp_i2s_start(void *opaque, int line, int level)
static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;

3
hw/omap.h
View file

@ -662,6 +662,9 @@ struct omap_mpu_state_s {
# error TARGET_PHYS_ADDR_BITS undefined
# endif
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
uint32_t value);
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value);

8
hw/omap_lcdc.c
View file

@ -114,7 +114,7 @@ static draw_line_func *draw_line_table2[33] = {
[32] = draw_line16_32,
};
void omap_update_display(void *opaque)
static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
draw_line_func *draw_line;
@ -289,7 +289,7 @@ static int ppm_save(const char *filename, uint8_t *data,
return 0;
}
void omap_screen_dump(void *opaque, const char *filename) {
static void omap_screen_dump(void *opaque, const char *filename) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_update_display(opaque);
if (omap_lcd && omap_lcd->state->data)
@ -298,12 +298,12 @@ void omap_screen_dump(void *opaque, const char *filename) {
omap_lcd->state->linesize);
}
void omap_invalidate_display(void *opaque) {
static void omap_invalidate_display(void *opaque) {
struct omap_lcd_panel_s *omap_lcd = opaque;
omap_lcd->invalidate = 1;
}
void omap_lcd_update(struct omap_lcd_panel_s *s) {
static void omap_lcd_update(struct omap_lcd_panel_s *s) {
if (!s->enable) {
s->dma->current_frame = -1;
s->sync_error = 0;

18
hw/parallel.c
View file

@ -458,45 +458,45 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
}
/* Memory mapped interface */
uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
}
void parallel_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void parallel_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}
uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}
void parallel_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void parallel_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}
uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
}
void parallel_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void parallel_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;

8
hw/pc.c
View file

@ -317,7 +317,7 @@ static uint32_t ioport92_read(void *opaque, uint32_t addr)
/***********************************************************/
/* Bochs BIOS debug ports */
void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
{
static const char shutdown_str[8] = "Shutdown";
static int shutdown_index = 0;
@ -361,7 +361,7 @@ void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
}
}
void bochs_bios_init(void)
static void bochs_bios_init(void)
{
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
@ -431,8 +431,8 @@ static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));
}
int load_kernel(const char *filename, uint8_t *addr,
uint8_t *real_addr)
static int load_kernel(const char *filename, uint8_t *addr,
uint8_t *real_addr)
{
int fd, size;
int setup_sects;

6
hw/pci.c
View file

@ -65,7 +65,7 @@ PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
return bus;
}
PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
{
PCIBus *bus;
bus = qemu_mallocz(sizeof(PCIBus));
@ -159,7 +159,7 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num,
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
}
target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
{
return addr + pci_mem_base;
}
@ -606,7 +606,7 @@ typedef struct {
PCIBus *bus;
} PCIBridge;
void pci_bridge_write_config(PCIDevice *d,
static void pci_bridge_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
PCIBridge *s = (PCIBridge *)d;

6
hw/pckbd.c
View file

@ -290,7 +290,7 @@ static uint32_t kbd_read_data(void *opaque, uint32_t addr)
return ps2_read_data(s->kbd);
}
void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
{
KBDState *s = opaque;
@ -385,7 +385,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
}
/* Memory mapped interface */
uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
{
KBDState *s = opaque;
@ -399,7 +399,7 @@ uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
}
}
void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
KBDState *s = opaque;

2
hw/piix_pci.c
View file

@ -314,7 +314,7 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id)
return pci_device_load(d, f);
}
int piix_init(PCIBus *bus, int devfn)
static int piix_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
uint8_t *pci_conf;

2
hw/pl061.c
View file

@ -209,7 +209,7 @@ static void pl061_reset(pl061_state *s)
s->cr = 0xff;
}
void pl061_set_irq(void * opaque, int irq, int level)
static void pl061_set_irq(void * opaque, int irq, int level)
{
pl061_state *s = (pl061_state *)opaque;
uint8_t mask;

2
hw/pl190.c
View file

@ -216,7 +216,7 @@ static CPUWriteMemoryFunc *pl190_writefn[] = {
pl190_write
};
void pl190_reset(pl190_state *s)
static void pl190_reset(pl190_state *s)
{
int i;

2
hw/pxa2xx_lcd.c
View file

@ -882,7 +882,7 @@ static void pxa2xx_screen_dump(void *opaque, const char *filename)
/* TODO */
}
void pxa2xx_lcdc_orientation(void *opaque, int angle)
static void pxa2xx_lcdc_orientation(void *opaque, int angle)
{
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;

1
hw/pxa2xx_pcmcia.c
View file

@ -9,6 +9,7 @@
#include "hw.h"
#include "pcmcia.h"
#include "pxa.h"
struct pxa2xx_pcmcia_s {
struct pcmcia_socket_s slot;

2
hw/realview_gic.c
View file

@ -8,7 +8,7 @@
*/
#include "hw.h"
#include "arm-misc.h"
#include "primecell.h"
#define GIC_NIRQ 96
#define NCPU 1

11
hw/rtl8139.c
View file

@ -497,7 +497,7 @@ typedef struct RTL8139State {
} RTL8139State;
void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
{
DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
@ -543,7 +543,7 @@ void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
}
}
void prom9346_shift_clock(EEprom9346 *eeprom)
static void prom9346_shift_clock(EEprom9346 *eeprom)
{
int bit = eeprom->eedi?1:0;
@ -635,7 +635,7 @@ void prom9346_shift_clock(EEprom9346 *eeprom)
}
}
int prom9346_get_wire(RTL8139State *s)
static int prom9346_get_wire(RTL8139State *s)
{
EEprom9346 *eeprom = &s->eeprom;
if (!eeprom->eecs)
@ -644,7 +644,8 @@ int prom9346_get_wire(RTL8139State *s)
return eeprom->eedo;
}
void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
{
EEprom9346 *eeprom = &s->eeprom;
uint8_t old_eecs = eeprom->eecs;
@ -1448,7 +1449,7 @@ static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
return ret;
}
int rtl8139_config_writeable(RTL8139State *s)
static int rtl8139_config_writeable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{

8
hw/sd.c
View file

@ -308,8 +308,8 @@ static int sd_req_crc_validate(struct sd_request_s *req)
return sd_crc7(buffer, 5) != req->crc; /* TODO */
}
void sd_response_r1_make(SDState *sd,
uint8_t *response, uint32_t last_status)
static void sd_response_r1_make(SDState *sd,
uint8_t *response, uint32_t last_status)
{
uint32_t mask = CARD_STATUS_B ^ ILLEGAL_COMMAND;
uint32_t status;
@ -323,7 +323,7 @@ void sd_response_r1_make(SDState *sd,
response[3] = (status >> 0) & 0xff;
}
void sd_response_r3_make(SDState *sd, uint8_t *response)
static void sd_response_r3_make(SDState *sd, uint8_t *response)
{
response[0] = (sd->ocr >> 24) & 0xff;
response[1] = (sd->ocr >> 16) & 0xff;
@ -331,7 +331,7 @@ void sd_response_r3_make(SDState *sd, uint8_t *response)
response[3] = (sd->ocr >> 0) & 0xff;
}
void sd_response_r6_make(SDState *sd, uint8_t *response)
static void sd_response_r6_make(SDState *sd, uint8_t *response)
{
uint16_t arg;
uint16_t status;

6
hw/sh_serial.c
View file

@ -252,14 +252,14 @@ static void sh_serial_event(void *opaque, int event)
sh_serial_receive_break(s);
}
uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr)
{
sh_serial_state *s = opaque;
return sh_serial_ioport_read(s, addr - s->base);
}
void sh_serial_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void sh_serial_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
sh_serial_state *s = opaque;
sh_serial_ioport_write(s, addr - s->base, value);

2
hw/sh_timer.c
View file

@ -52,7 +52,7 @@ static void sh_timer_update(sh_timer_state *s)
#endif
}
uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;

2
hw/smbus.c
View file

@ -61,7 +61,7 @@ static void smbus_do_write(SMBusDevice *dev)
}
}
void smbus_i2c_event(i2c_slave *s, enum i2c_event event)
static void smbus_i2c_event(i2c_slave *s, enum i2c_event event)
{
SMBusDevice *dev = (SMBusDevice *)s;
switch (event) {

2
hw/stellaris.c
View file

@ -521,7 +521,7 @@ static CPUWriteMemoryFunc *ssys_writefn[] = {
ssys_write
};
void ssys_reset(void *opaque)
static void ssys_reset(void *opaque)
{
ssys_state *s = (ssys_state *)opaque;

1
hw/usb-ohci.c
View file

@ -31,6 +31,7 @@
#include "qemu-timer.h"
#include "usb.h"
#include "pci.h"
#include "pxa.h"
//#define DEBUG_OHCI
/* Dump packet contents. */

6
hw/wm8750.c
View file

@ -124,7 +124,7 @@ static const struct wm_rate_s wm_rate_table[] = {
{ 192, 88200, 128, 88200 }, /* SR: 11111 */
};
void wm8750_set_format(struct wm8750_s *s)
static void wm8750_set_format(struct wm8750_s *s)
{
int i;
audsettings_t in_fmt;
@ -194,7 +194,7 @@ void wm8750_set_format(struct wm8750_s *s)
AUD_set_active_out(*s->out[0], 1);
}
void inline wm8750_mask_update(struct wm8750_s *s)
static void inline wm8750_mask_update(struct wm8750_s *s)
{
#define R_ONLY 0x0000ffff
#define L_ONLY 0xffff0000
@ -596,7 +596,7 @@ i2c_slave *wm8750_init(i2c_bus *bus, AudioState *audio)
return &s->i2c;
}
void wm8750_fini(i2c_slave *i2c)
static void wm8750_fini(i2c_slave *i2c)
{
struct wm8750_s *s = (struct wm8750_s *) i2c;
wm8750_reset(&s->i2c);

23
i386-dis.c
View file

@ -1838,29 +1838,6 @@ static char close_char;
static char separator_char;
static char scale_char;
/* Here for backwards compatibility. When gdb stops using
print_insn_i386_att and print_insn_i386_intel these functions can
disappear, and print_insn_i386 be merged into print_insn. */
int
print_insn_i386_att (pc, info)
bfd_vma pc;
disassemble_info *info;
{
intel_syntax = 0;
return print_insn (pc, info);
}
int
print_insn_i386_intel (pc, info)
bfd_vma pc;
disassemble_info *info;
{
intel_syntax = 1;
return print_insn (pc, info);
}
int
print_insn_i386 (pc, info)
bfd_vma pc;

1
loader.c
View file

@ -23,6 +23,7 @@
*/
#include "qemu-common.h"
#include "disas.h"
#include "sysemu.h"
#include "uboot_image.h"
/* return the size or -1 if error */

4
monitor.c
View file

@ -261,7 +261,7 @@ static void do_info_block(void)
}
/* get the current CPU defined by the user */
int mon_set_cpu(int cpu_index)
static int mon_set_cpu(int cpu_index)
{
CPUState *env;
@ -274,7 +274,7 @@ int mon_set_cpu(int cpu_index)
return -1;
}
CPUState *mon_get_cpu(void)
static CPUState *mon_get_cpu(void)
{
if (!mon_cpu) {
mon_set_cpu(0);

4
osdep.c
View file

@ -82,7 +82,7 @@ void qemu_vfree(void *ptr)
#include <sys/mman.h>
#include <fcntl.h>
void *kqemu_vmalloc(size_t size)
static void *kqemu_vmalloc(size_t size)
{
static int phys_ram_fd = -1;
static int phys_ram_size = 0;
@ -164,7 +164,7 @@ void *kqemu_vmalloc(size_t size)
return ptr;
}
void kqemu_vfree(void *ptr)
static void kqemu_vfree(void *ptr)
{
/* may be useful some day, but currently we do not need to free */
}

1
qemu-char.h
View file

@ -46,6 +46,7 @@ struct CharDriverState {
};
CharDriverState *qemu_chr_open(const char *filename);
void qemu_chr_close(CharDriverState *chr);
void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
void qemu_chr_send_event(CharDriverState *s, int event);

4
target-i386/helper.c
View file

@ -1235,7 +1235,7 @@ void do_interrupt(int intno, int is_int, int error_code,
* needed. It should only be called, if this is not an interrupt.
* Returns the new exception number.
*/
int check_exception(int intno, int *error_code)
static int check_exception(int intno, int *error_code)
{
char first_contributory = env->old_exception == 0 ||
(env->old_exception >= 10 &&
@ -3051,7 +3051,7 @@ void helper_fstt_ST0_A0(void)
helper_fstt(ST0, A0);
}
void fpu_set_exception(int mask)
static void fpu_set_exception(int mask)
{
env->fpus |= mask;
if (env->fpus & (~env->fpuc & FPUC_EM))

3
translate-op.c
View file

@ -33,5 +33,8 @@ enum {
};
#include "dyngen.h"
extern int dyngen_code(uint8_t *gen_code_buf,
uint16_t *label_offsets, uint16_t *jmp_offsets,
const uint16_t *opc_buf, const uint32_t *opparam_buf, const long *gen_labels);
#include "op.h"

8
usb-linux.c
View file

@ -907,10 +907,10 @@ static const char *usb_class_str(uint8_t class)
return p->class_name;
}
void usb_info_device(int bus_num, int addr, int class_id,
int vendor_id, int product_id,
const char *product_name,
int speed)
static void usb_info_device(int bus_num, int addr, int class_id,
int vendor_id, int product_id,
const char *product_name,
int speed)
{
const char *class_str, *speed_str;

39
vl.c
View file

@ -242,7 +242,7 @@ const char *prom_envs[MAX_PROM_ENVS];
target_phys_addr_t isa_mem_base = 0;
PicState2 *isa_pic;
uint32_t default_ioport_readb(void *opaque, uint32_t address)
static uint32_t default_ioport_readb(void *opaque, uint32_t address)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused inb: port=0x%04x\n", address);
@ -250,7 +250,7 @@ uint32_t default_ioport_readb(void *opaque, uint32_t address)
return 0xff;
}
void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused outb: port=0x%04x data=0x%02x\n", address, data);
@ -258,7 +258,7 @@ void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
}
/* default is to make two byte accesses */
uint32_t default_ioport_readw(void *opaque, uint32_t address)
static uint32_t default_ioport_readw(void *opaque, uint32_t address)
{
uint32_t data;
data = ioport_read_table[0][address](ioport_opaque[address], address);
@ -267,14 +267,14 @@ uint32_t default_ioport_readw(void *opaque, uint32_t address)
return data;
}
void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
{
ioport_write_table[0][address](ioport_opaque[address], address, data & 0xff);
address = (address + 1) & (MAX_IOPORTS - 1);
ioport_write_table[0][address](ioport_opaque[address], address, (data >> 8) & 0xff);
}
uint32_t default_ioport_readl(void *opaque, uint32_t address)
static uint32_t default_ioport_readl(void *opaque, uint32_t address)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused inl: port=0x%04x\n", address);
@ -282,14 +282,14 @@ uint32_t default_ioport_readl(void *opaque, uint32_t address)
return 0xffffffff;
}
void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
{
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "unused outl: port=0x%04x data=0x%02x\n", address, data);
#endif
}
void init_ioports(void)
static void init_ioports(void)
{
int i;
@ -961,7 +961,7 @@ QEMUClock *vm_clock;
static QEMUTimer *active_timers[2];
QEMUClock *qemu_new_clock(int type)
static QEMUClock *qemu_new_clock(int type)
{
QEMUClock *clock;
clock = qemu_mallocz(sizeof(QEMUClock));
@ -1539,7 +1539,7 @@ static void init_timer_alarm(void)
alarm_timer = t;
}
void quit_timers(void)
static void quit_timers(void)
{
alarm_timer->stop(alarm_timer);
alarm_timer = NULL;
@ -1832,7 +1832,7 @@ static void mux_chr_update_read_handler(CharDriverState *chr)
d->mux_cnt++;
}
CharDriverState *qemu_chr_open_mux(CharDriverState *drv)
static CharDriverState *qemu_chr_open_mux(CharDriverState *drv)
{
CharDriverState *chr;
MuxDriver *d;
@ -3385,7 +3385,7 @@ void qemu_chr_close(CharDriverState *chr)
/***********************************************************/
/* network device redirectors */
void hex_dump(FILE *f, const uint8_t *buf, int size)
static void hex_dump(FILE *f, const uint8_t *buf, int size)
{
int len, i, j, c;
@ -3733,7 +3733,7 @@ static void smb_exit(void)
}
/* automatic user mode samba server configuration */
void net_slirp_smb(const char *exported_dir)
static void net_slirp_smb(const char *exported_dir)
{
char smb_conf[1024];
char smb_cmdline[1024];
@ -5127,7 +5127,7 @@ QEMUFile *qemu_fopen(const char *filename, const char *mode)
return NULL;
}
QEMUFile *qemu_fopen_bdrv(BlockDriverState *bs, int64_t offset, int is_writable)
static QEMUFile *qemu_fopen_bdrv(BlockDriverState *bs, int64_t offset, int is_writable)
{
QEMUFile *f;
@ -5361,7 +5361,7 @@ int register_savevm(const char *idstr,
#define QEMU_VM_FILE_MAGIC 0x5145564d
#define QEMU_VM_FILE_VERSION 0x00000002
int qemu_savevm_state(QEMUFile *f)
static int qemu_savevm_state(QEMUFile *f)
{
SaveStateEntry *se;
int len, ret;
@ -5384,7 +5384,6 @@ int qemu_savevm_state(QEMUFile *f)
/* record size: filled later */
len_pos = qemu_ftell(f);
qemu_put_be32(f, 0);
se->save_state(f, se->opaque);
/* fill record size */
@ -5415,7 +5414,7 @@ static SaveStateEntry *find_se(const char *idstr, int instance_id)
return NULL;
}
int qemu_loadvm_state(QEMUFile *f)
static int qemu_loadvm_state(QEMUFile *f)
{
SaveStateEntry *se;
int len, ret, instance_id, record_len, version_id;
@ -6655,7 +6654,7 @@ int qemu_register_machine(QEMUMachine *m)
return 0;
}
QEMUMachine *find_machine(const char *name)
static QEMUMachine *find_machine(const char *name)
{
QEMUMachine *m;
@ -6669,7 +6668,7 @@ QEMUMachine *find_machine(const char *name)
/***********************************************************/
/* main execution loop */
void gui_update(void *opaque)
static void gui_update(void *opaque)
{
DisplayState *ds = opaque;
ds->dpy_refresh(ds);
@ -6953,7 +6952,7 @@ void main_loop_wait(int timeout)
static CPUState *cur_cpu;
int main_loop(void)
static int main_loop(void)
{
int ret, timeout;
#ifdef CONFIG_PROFILER
@ -7414,7 +7413,7 @@ static void read_passwords(void)
}
/* XXX: currently we cannot use simultaneously different CPUs */
void register_machines(void)
static void register_machines(void)
{
#if defined(TARGET_I386)
qemu_register_machine(&pc_machine);

12
vnc.c
View file

@ -812,9 +812,9 @@ static uint32_t read_u32(uint8_t *data, size_t offset)
}
#if CONFIG_VNC_TLS
ssize_t vnc_tls_push(gnutls_transport_ptr_t transport,
const void *data,
size_t len) {
static ssize_t vnc_tls_push(gnutls_transport_ptr_t transport,
const void *data,
size_t len) {
struct VncState *vs = (struct VncState *)transport;
int ret;
@ -829,9 +829,9 @@ ssize_t vnc_tls_push(gnutls_transport_ptr_t transport,
}
ssize_t vnc_tls_pull(gnutls_transport_ptr_t transport,
void *data,
size_t len) {
static ssize_t vnc_tls_pull(gnutls_transport_ptr_t transport,
void *data,
size_t len) {
struct VncState *vs = (struct VncState *)transport;
int ret;

1
x_keymap.c
View file

@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "qemu-common.h"
#include "console.h"
static const uint8_t x_keycode_to_pc_keycode[115] = {
0xc7, /* 97 Home */