target-lm32: fix LOG_DIS operand order
The order of most opcodes with immediates was wrong (according to the reference manual) in the (debug) logging. Additionally, one operand for the andhi instruction was completly wrong. Fix these. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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@ -211,7 +211,7 @@ static void dec_and(DisasContext *dc)
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static void dec_andhi(DisasContext *dc)
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static void dec_andhi(DisasContext *dc)
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{
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{
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LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
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LOG_DIS("andhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
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}
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}
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@ -274,7 +274,7 @@ static inline void gen_cond_branch(DisasContext *dc, int cond)
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static void dec_be(DisasContext *dc)
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static void dec_be(DisasContext *dc)
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{
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{
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LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("be r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16) * 4);
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sign_extend(dc->imm16, 16) * 4);
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gen_cond_branch(dc, TCG_COND_EQ);
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gen_cond_branch(dc, TCG_COND_EQ);
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@ -282,7 +282,7 @@ static void dec_be(DisasContext *dc)
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static void dec_bg(DisasContext *dc)
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static void dec_bg(DisasContext *dc)
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{
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{
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LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("bg r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16 * 4));
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sign_extend(dc->imm16, 16 * 4));
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gen_cond_branch(dc, TCG_COND_GT);
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gen_cond_branch(dc, TCG_COND_GT);
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@ -290,7 +290,7 @@ static void dec_bg(DisasContext *dc)
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static void dec_bge(DisasContext *dc)
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static void dec_bge(DisasContext *dc)
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{
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{
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LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("bge r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16) * 4);
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sign_extend(dc->imm16, 16) * 4);
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gen_cond_branch(dc, TCG_COND_GE);
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gen_cond_branch(dc, TCG_COND_GE);
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@ -298,7 +298,7 @@ static void dec_bge(DisasContext *dc)
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static void dec_bgeu(DisasContext *dc)
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static void dec_bgeu(DisasContext *dc)
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{
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{
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LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("bgeu r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16) * 4);
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sign_extend(dc->imm16, 16) * 4);
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gen_cond_branch(dc, TCG_COND_GEU);
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gen_cond_branch(dc, TCG_COND_GEU);
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@ -306,7 +306,7 @@ static void dec_bgeu(DisasContext *dc)
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static void dec_bgu(DisasContext *dc)
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static void dec_bgu(DisasContext *dc)
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{
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{
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LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("bgu r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16) * 4);
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sign_extend(dc->imm16, 16) * 4);
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gen_cond_branch(dc, TCG_COND_GTU);
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gen_cond_branch(dc, TCG_COND_GTU);
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@ -314,7 +314,7 @@ static void dec_bgu(DisasContext *dc)
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static void dec_bne(DisasContext *dc)
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static void dec_bne(DisasContext *dc)
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{
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{
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LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("bne r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16) * 4);
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sign_extend(dc->imm16, 16) * 4);
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gen_cond_branch(dc, TCG_COND_NE);
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gen_cond_branch(dc, TCG_COND_NE);
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@ -367,7 +367,7 @@ static inline void gen_compare(DisasContext *dc, int cond)
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static void dec_cmpe(DisasContext *dc)
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static void dec_cmpe(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpei r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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sign_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -379,7 +379,7 @@ static void dec_cmpe(DisasContext *dc)
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static void dec_cmpg(DisasContext *dc)
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static void dec_cmpg(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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sign_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -391,7 +391,7 @@ static void dec_cmpg(DisasContext *dc)
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static void dec_cmpge(DisasContext *dc)
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static void dec_cmpge(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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sign_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -403,7 +403,7 @@ static void dec_cmpge(DisasContext *dc)
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static void dec_cmpgeu(DisasContext *dc)
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static void dec_cmpgeu(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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zero_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -415,7 +415,7 @@ static void dec_cmpgeu(DisasContext *dc)
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static void dec_cmpgu(DisasContext *dc)
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static void dec_cmpgu(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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zero_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -427,7 +427,7 @@ static void dec_cmpgu(DisasContext *dc)
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static void dec_cmpne(DisasContext *dc)
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static void dec_cmpne(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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sign_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -539,7 +539,7 @@ static void dec_modu(DisasContext *dc)
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static void dec_mul(DisasContext *dc)
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static void dec_mul(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("muli r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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sign_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -563,7 +563,7 @@ static void dec_mul(DisasContext *dc)
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static void dec_nor(DisasContext *dc)
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static void dec_nor(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("nori r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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zero_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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@ -959,7 +959,7 @@ static void dec_wcsr(DisasContext *dc)
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static void dec_xnor(DisasContext *dc)
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static void dec_xnor(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("xnori r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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zero_extend(dc->imm16, 16));
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} else {
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} else {
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if (dc->r1 == R_R0) {
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if (dc->r1 == R_R0) {
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@ -981,7 +981,7 @@ static void dec_xnor(DisasContext *dc)
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static void dec_xor(DisasContext *dc)
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static void dec_xor(DisasContext *dc)
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{
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{
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if (dc->format == OP_FMT_RI) {
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
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LOG_DIS("xori r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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zero_extend(dc->imm16, 16));
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} else {
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} else {
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LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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