target-i386: Move xsave component mask to features array
This will reuse the existing check/enforce logic in x86_cpu_filter_features() to check the xsave component bits against GET_SUPPORTED_CPUID. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -489,6 +489,18 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.cpuid_eax = 6, .cpuid_reg = R_EAX,
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.tcg_features = TCG_6_EAX_FEATURES,
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},
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[FEAT_XSAVE_COMP_LO] = {
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.cpuid_eax = 0xD,
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.cpuid_needs_ecx = true, .cpuid_ecx = 0,
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.cpuid_reg = R_EAX,
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.tcg_features = ~0U,
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},
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[FEAT_XSAVE_COMP_HI] = {
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.cpuid_eax = 0xD,
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.cpuid_needs_ecx = true, .cpuid_ecx = 0,
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.cpuid_reg = R_EDX,
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.tcg_features = ~0U,
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},
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};
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typedef struct X86RegisterInfo32 {
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@ -562,6 +574,12 @@ static uint32_t xsave_area_size(uint64_t mask)
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return ret;
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}
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static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
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{
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return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
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cpu->env.features[FEAT_XSAVE_COMP_LO];
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}
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const char *get_register_name_32(unsigned int reg)
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{
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if (reg >= CPU_NB_REGS32) {
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@ -2514,15 +2532,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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if (count == 0) {
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*ecx = xsave_area_size(env->xsave_components);
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*eax = env->xsave_components;
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*edx = env->xsave_components >> 32;
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*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
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*eax = env->features[FEAT_XSAVE_COMP_LO];
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*edx = env->features[FEAT_XSAVE_COMP_HI];
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*ebx = *ecx;
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} else if (count == 1) {
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*eax = env->features[FEAT_XSAVE];
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} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
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const ExtSaveArea *esa = &x86_ext_save_areas[count];
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if ((env->xsave_components >> count) & 1) {
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if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
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const ExtSaveArea *esa = &x86_ext_save_areas[count];
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*eax = esa->size;
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*ebx = esa->offset;
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}
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@ -2957,26 +2975,22 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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int i;
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uint64_t mask;
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if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
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return;
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}
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env->xsave_components = (XSTATE_FP_MASK | XSTATE_SSE_MASK);
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mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK);
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for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
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const ExtSaveArea *esa = &x86_ext_save_areas[i];
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if (env->features[esa->feature] & esa->bits) {
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env->xsave_components |= (1ULL << i);
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mask |= (1ULL << i);
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}
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}
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if (kvm_enabled()) {
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KVMState *s = kvm_state;
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uint64_t kvm_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
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kvm_mask <<= 32;
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kvm_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
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env->xsave_components &= kvm_mask;
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}
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env->features[FEAT_XSAVE_COMP_LO] = mask;
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env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
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}
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#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
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@ -453,6 +453,8 @@ typedef enum FeatureWord {
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FEAT_SVM, /* CPUID[8000_000A].EDX */
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FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
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FEAT_6_EAX, /* CPUID[6].EAX */
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FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
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FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
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FEATURE_WORDS,
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} FeatureWord;
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@ -1122,7 +1124,6 @@ typedef struct CPUX86State {
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uint32_t cpuid_vendor3;
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uint32_t cpuid_version;
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FeatureWordArray features;
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uint64_t xsave_components;
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uint32_t cpuid_model[12];
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/* MTRRs */
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