target/arm: don't bother with id_aa64pfr0_read for USER_ONLY
For system emulation we need to check the state of the GIC before we report the value. However this isn't relevant to exporting of the value to linux-user and indeed breaks the exported value as set by modify_arm_cp_regs. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200316172155.971-20-alex.bennee@linaro.org>
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@ -6697,6 +6697,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return pfr1;
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}
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#ifndef CONFIG_USER_ONLY
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static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -6707,6 +6708,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
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}
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return pfr0;
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}
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#endif
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/* Shared logic between LORID and the rest of the LOR* registers.
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* Secure state has already been delt with.
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@ -7280,16 +7282,24 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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* define new registers here.
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*/
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ARMCPRegInfo v8_idregs[] = {
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/* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
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* know the right value for the GIC field until after we
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* define these regs.
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/*
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* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
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* emulation because we don't know the right value for the
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* GIC field until after we define these regs.
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*/
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{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_NO_RAW,
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.access = PL1_R,
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#ifdef CONFIG_USER_ONLY
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.type = ARM_CP_CONST,
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.resetvalue = cpu->isar.id_aa64pfr0
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#else
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.type = ARM_CP_NO_RAW,
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.accessfn = access_aa64_tid3,
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.readfn = id_aa64pfr0_read,
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.writefn = arm_cp_write_ignore },
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.writefn = arm_cp_write_ignore
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#endif
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},
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{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
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.access = PL1_R, .type = ARM_CP_CONST,
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