spapr/xive: Set the OS CAM line at reset
When a Virtual Processor is scheduled to run on a HW thread, the hypervisor pushes its identifier in the OS CAM line. When running with kernel_irqchip=off, QEMU needs to emulate the same behavior. Set the OS CAM line when the interrupt presenter of the sPAPR core is reset. This will also cover the case of hot-plugged CPUs. This change also has the benefit to remove the use of CPU_FOREACH() which can be unsafe. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20191022163812.330-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -205,23 +205,6 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable)
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memory_region_set_enabled(&xive->end_source.esb_mmio, false);
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memory_region_set_enabled(&xive->end_source.esb_mmio, false);
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}
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}
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/*
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* When a Virtual Processor is scheduled to run on a HW thread, the
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* hypervisor pushes its identifier in the OS CAM line. Emulate the
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* same behavior under QEMU.
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*/
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void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx)
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{
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uint8_t nvt_blk;
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uint32_t nvt_idx;
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uint32_t nvt_cam;
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spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx);
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nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx));
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4);
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}
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static void spapr_xive_end_reset(XiveEND *end)
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static void spapr_xive_end_reset(XiveEND *end)
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{
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{
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memset(end, 0, sizeof(*end));
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memset(end, 0, sizeof(*end));
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@ -544,21 +527,32 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc,
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}
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}
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spapr_cpu->tctx = XIVE_TCTX(obj);
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spapr_cpu->tctx = XIVE_TCTX(obj);
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/*
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* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
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* don't beneficiate from the reset of the XIVE IRQ backend
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*/
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spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
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return 0;
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return 0;
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}
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}
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static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t os_cam)
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{
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uint32_t qw1w2 = cpu_to_be32(TM_QW1W2_VO | os_cam);
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
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}
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static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc,
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static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc,
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PowerPCCPU *cpu)
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PowerPCCPU *cpu)
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{
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{
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XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
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XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
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uint8_t nvt_blk;
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uint32_t nvt_idx;
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xive_tctx_reset(tctx);
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xive_tctx_reset(tctx);
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/*
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* When a Virtual Processor is scheduled to run on a HW thread,
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* the hypervisor pushes its identifier in the OS CAM line.
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* Emulate the same behavior under QEMU.
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*/
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spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx);
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xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx));
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}
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}
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static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val)
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static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val)
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@ -651,14 +645,6 @@ static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers,
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static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp)
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static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp)
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{
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{
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SpaprXive *xive = SPAPR_XIVE(intc);
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SpaprXive *xive = SPAPR_XIVE(intc);
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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/* (TCG) Set the OS CAM line of the thread interrupt context. */
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spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
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}
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if (kvm_enabled()) {
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if (kvm_enabled()) {
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int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp);
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int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp);
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@ -57,7 +57,6 @@ typedef struct SpaprXive {
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void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
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void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
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void spapr_xive_hcall_init(SpaprMachineState *spapr);
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void spapr_xive_hcall_init(SpaprMachineState *spapr);
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void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);
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void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
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void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
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void spapr_xive_map_mmio(SpaprXive *xive);
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void spapr_xive_map_mmio(SpaprXive *xive);
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