target-ppc: Introduce DFP Round to Integer
Add emulation of the PowerPC Decimal Floating Point (DFP) Round to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP Integer Without Inexact (drintn[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -800,3 +800,43 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, \
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DFP_HELPER_RRND(drrnd, 64)
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DFP_HELPER_RRND(drrnd, 64)
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DFP_HELPER_RRND(drrndq, 128)
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DFP_HELPER_RRND(drrndq, 128)
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#define DFP_HELPER_RINT(op, postprocs, size) \
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void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b, \
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uint32_t r, uint32_t rmc) \
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{ \
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struct PPC_DFP dfp; \
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\
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dfp_prepare_decimal##size(&dfp, 0, b, env); \
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\
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dfp_set_round_mode_from_immediate(r, rmc, &dfp); \
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decNumberToIntegralExact(&dfp.t, &dfp.b, &dfp.context); \
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decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, &dfp.context); \
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postprocs(&dfp); \
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\
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if (size == 64) { \
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t[0] = dfp.t64[0]; \
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} else if (size == 128) { \
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t[0] = dfp.t64[HI_IDX]; \
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t[1] = dfp.t64[LO_IDX]; \
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} \
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}
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static void RINTX_PPs(struct PPC_DFP *dfp)
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{
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dfp_set_FPRF_from_FRT(dfp);
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dfp_check_for_XX(dfp);
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dfp_check_for_VXSNAN(dfp);
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}
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DFP_HELPER_RINT(drintx, RINTX_PPs, 64)
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DFP_HELPER_RINT(drintxq, RINTX_PPs, 128)
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static void RINTN_PPs(struct PPC_DFP *dfp)
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{
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dfp_set_FPRF_from_FRT(dfp);
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dfp_check_for_VXSNAN(dfp);
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}
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DFP_HELPER_RINT(drintn, RINTN_PPs, 64)
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DFP_HELPER_RINT(drintnq, RINTN_PPs, 128)
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@ -642,3 +642,7 @@ DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drintx, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintxq, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintn, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintnq, void, env, fprp, fprp, i32, i32)
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@ -8382,6 +8382,10 @@ GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
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GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
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GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
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/*** SPE extension ***/
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/*** SPE extension ***/
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/* Register moves */
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/* Register moves */
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@ -11335,6 +11339,10 @@ GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
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GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
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GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
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GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
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GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
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GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
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GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
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GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
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GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
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GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
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GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
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#undef GEN_SPE
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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