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target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree

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Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-27-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-25 18:08:24 +02:00
parent 2f2745c81a
commit 97fe675519
2 changed files with 18 additions and 87 deletions
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2
target/mips/tcg/msa.decode
View file

@ -167,7 +167,9 @@ BNZ 010001 111 .. ..... ................ @bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w

103
target/mips/tcg/msa_translate.c
View file

@ -46,9 +46,7 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@ -631,98 +629,31 @@ static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
return trans_msa_elm_fn(ctx, a, gen_msa_copy_u);
}
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
static gen_helper_piii * const gen_msa_copy_s[4] = {
gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h,
gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d)
};
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
return trans_msa_elm_fn(ctx, a, gen_msa_copy_s);
}
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
case OPC_INSERT_df:
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
if (df == DF_DOUBLE) {
gen_reserved_instruction(ctx);
break;
}
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
switch (df) {
case DF_BYTE:
gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
break;
case DF_HALF:
gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
break;
case DF_WORD:
gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
break;
#if defined(TARGET_MIPS64)
case DF_DOUBLE:
gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);
}
}
break;
case OPC_INSERT_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
break;
case DF_HALF:
gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
break;
case DF_WORD:
gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
break;
#if defined(TARGET_MIPS64)
case DF_DOUBLE:
gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);
}
break;
}
break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
}
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(tn);
static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a)
{
static gen_helper_piii * const gen_msa_insert[4] = {
gen_helper_msa_insert_b, gen_helper_msa_insert_h,
gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d)
};
return trans_msa_elm_fn(ctx, a, gen_msa_insert);
}
static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
uint32_t df = 0, n = 0;
if ((dfn & 0x30) == 0x00) {
n = dfn & 0x0f;
df = DF_BYTE;
} else if ((dfn & 0x38) == 0x20) {
n = dfn & 0x07;
df = DF_HALF;
} else if ((dfn & 0x3c) == 0x30) {
n = dfn & 0x03;
df = DF_WORD;
} else if ((dfn & 0x3e) == 0x38) {
n = dfn & 0x01;
df = DF_DOUBLE;
} else if (dfn == 0x3E) {
if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
gen_msa_elm_3e(ctx);
return;
@ -730,8 +661,6 @@ static void gen_msa_elm(DisasContext *ctx)
gen_reserved_instruction(ctx);
return;
}
gen_msa_elm_df(ctx, df, n);
}
TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df);