diff --git a/hw/omap_gptimer.c b/hw/omap_gptimer.c index c1cbdf8dcf..414b98aa36 100644 --- a/hw/omap_gptimer.c +++ b/hw/omap_gptimer.c @@ -23,6 +23,7 @@ /* GP timers */ struct omap_gp_timer_s { + MemoryRegion iomem; qemu_irq irq; qemu_irq wkup; qemu_irq in; @@ -337,12 +338,6 @@ static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) } } -static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = { - omap_badwidth_read32, - omap_gp_timer_readh, - omap_gp_timer_readw, -}; - static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, uint32_t value) { @@ -454,16 +449,25 @@ static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, s->writeh = (uint16_t) value; } -static CPUWriteMemoryFunc * const omap_gp_timer_writefn[] = { - omap_badwidth_write32, - omap_gp_timer_writeh, - omap_gp_timer_write, +static const MemoryRegionOps omap_gp_timer_ops = { + .old_mmio = { + .read = { + omap_badwidth_read32, + omap_gp_timer_readh, + omap_gp_timer_readw, + }, + .write = { + omap_badwidth_write32, + omap_gp_timer_writeh, + omap_gp_timer_write, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, qemu_irq irq, omap_clk fclk, omap_clk iclk) { - int iomemtype; struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) g_malloc0(sizeof(struct omap_gp_timer_s)); @@ -476,9 +480,9 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, omap_gp_timer_reset(s); omap_gp_timer_clk_setup(s); - iomemtype = cpu_register_io_memory(omap_gp_timer_readfn, - omap_gp_timer_writefn, s, DEVICE_NATIVE_ENDIAN); - omap_l4_attach(ta, 0, iomemtype); + memory_region_init_io(&s->iomem, &omap_gp_timer_ops, s, "omap.gptimer", + omap_l4_region_size(ta, 0)); + omap_l4_attach_region(ta, 0, &s->iomem); return s; }