Simplify branch likely handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2676 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -1455,12 +1455,11 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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gen_op_goto_tb1(TBPARAM(tb));
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gen_op_goto_tb1(TBPARAM(tb));
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gen_op_save_pc(dest);
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gen_op_save_pc(dest);
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gen_op_set_T0((long)tb + n);
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gen_op_set_T0((long)tb + n);
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gen_op_exit_tb();
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} else {
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} else {
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gen_op_save_pc(dest);
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gen_op_save_pc(dest);
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gen_op_set_T0(0);
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gen_op_reset_T0();
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gen_op_exit_tb();
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}
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}
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gen_op_exit_tb();
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}
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}
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/* Branches (before delay slot) */
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/* Branches (before delay slot) */
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@ -1565,18 +1564,21 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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case OPC_BLTZAL: /* 0 < 0 */
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case OPC_BLTZAL: /* 0 < 0 */
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gen_op_set_T0(ctx->pc + 8);
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gen_op_set_T0(ctx->pc + 8);
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gen_op_store_T0_gpr(31);
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gen_op_store_T0_gpr(31);
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MIPS_DEBUG("bnever and link");
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return;
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return;
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case OPC_BLTZALL: /* 0 < 0 likely */
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case OPC_BLTZALL: /* 0 < 0 likely */
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gen_op_set_T0(ctx->pc + 8);
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gen_op_set_T0(ctx->pc + 8);
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gen_op_store_T0_gpr(31);
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gen_op_store_T0_gpr(31);
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gen_goto_tb(ctx, 0, ctx->pc + 8);
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/* Skip the instruction in the delay slot */
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MIPS_DEBUG("bnever, link and skip");
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ctx->pc += 4;
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return;
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return;
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case OPC_BNEL: /* rx != rx likely */
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case OPC_BNEL: /* rx != rx likely */
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case OPC_BGTZL: /* 0 > 0 likely */
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case OPC_BGTZL: /* 0 > 0 likely */
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case OPC_BLTZL: /* 0 < 0 likely */
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case OPC_BLTZL: /* 0 < 0 likely */
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/* Skip the instruction in the delay slot */
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/* Skip the instruction in the delay slot */
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MIPS_DEBUG("bnever and skip");
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MIPS_DEBUG("bnever and skip");
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gen_goto_tb(ctx, 0, ctx->pc + 8);
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ctx->pc += 4;
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return;
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return;
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case OPC_J:
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case OPC_J:
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ctx->hflags |= MIPS_HFLAG_B;
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ctx->hflags |= MIPS_HFLAG_B;
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