target/ppc: rewrite f[n]m[add,sub] using float64_muladd
Use the softfloat api for fused multiply-add. Introduce routine to set the FPSCR flags VXNAN, VXIMZ nad VMISI. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania
David Gibson
parent
ec975e839c
commit
992d7e976c
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@ -743,178 +743,62 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
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return do_fri(env, arg, float_round_down);
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}
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/* fmadd - fmadd. */
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uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
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uint64_t arg3)
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static void float64_maddsub_update_excp(CPUPPCState *env, float64 arg1,
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float64 arg2, float64 arg3,
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unsigned int madd_flags)
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{
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CPU_DoubleU farg1, farg2, farg3;
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
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(float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
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if (unlikely((float64_is_infinity(arg1) && float64_is_zero(arg2)) ||
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(float64_is_zero(arg1) && float64_is_infinity(arg2)))) {
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/* Multiplication of zero by infinity */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else {
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if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
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float64_is_signaling_nan(farg2.d, &env->fp_status) ||
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float64_is_signaling_nan(farg3.d, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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}
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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arg1 = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else if (unlikely(float64_is_signaling_nan(arg1, &env->fp_status) ||
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float64_is_signaling_nan(arg2, &env->fp_status) ||
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float64_is_signaling_nan(arg3, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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} else if ((float64_is_infinity(arg1) || float64_is_infinity(arg2)) &&
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float64_is_infinity(arg3)) {
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uint8_t aSign, bSign, cSign;
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ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
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ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
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ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
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if (unlikely(float128_is_infinity(ft0_128) &&
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float64_is_infinity(farg3.d) &&
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float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
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/* Magnitude subtraction of infinities */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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} else {
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ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
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ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
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farg1.d = float128_to_float64(ft0_128, &env->fp_status);
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aSign = float64_is_neg(arg1);
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bSign = float64_is_neg(arg2);
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cSign = float64_is_neg(arg3);
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if (madd_flags & float_muladd_negate_c) {
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cSign ^= 1;
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}
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if (aSign ^ bSign ^ cSign) {
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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}
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}
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return farg1.ll;
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}
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/* fmsub - fmsub. */
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uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
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uint64_t arg3)
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{
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CPU_DoubleU farg1, farg2, farg3;
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
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(float64_is_zero(farg1.d) &&
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float64_is_infinity(farg2.d)))) {
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/* Multiplication of zero by infinity */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else {
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if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
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float64_is_signaling_nan(farg2.d, &env->fp_status) ||
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float64_is_signaling_nan(farg3.d, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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}
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
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ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
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ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
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if (unlikely(float128_is_infinity(ft0_128) &&
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float64_is_infinity(farg3.d) &&
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float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
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/* Magnitude subtraction of infinities */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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} else {
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ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
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ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
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farg1.d = float128_to_float64(ft0_128, &env->fp_status);
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}
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}
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return farg1.ll;
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#define FPU_FMADD(op, madd_flags) \
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uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
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uint64_t arg2, uint64_t arg3) \
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{ \
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uint32_t flags; \
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float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
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&env->fp_status); \
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flags = get_float_exception_flags(&env->fp_status); \
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if (flags) { \
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if (flags & float_flag_invalid) { \
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float64_maddsub_update_excp(env, arg1, arg2, arg3, \
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madd_flags); \
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} \
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float_check_status(env); \
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} \
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return ret; \
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}
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/* fnmadd - fnmadd. */
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uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
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uint64_t arg3)
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{
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CPU_DoubleU farg1, farg2, farg3;
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#define MADD_FLGS 0
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#define MSUB_FLGS float_muladd_negate_c
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#define NMADD_FLGS float_muladd_negate_result
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#define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
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(float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
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/* Multiplication of zero by infinity */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else {
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if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
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float64_is_signaling_nan(farg2.d, &env->fp_status) ||
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float64_is_signaling_nan(farg3.d, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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}
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
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ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
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ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
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if (unlikely(float128_is_infinity(ft0_128) &&
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float64_is_infinity(farg3.d) &&
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float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
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/* Magnitude subtraction of infinities */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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} else {
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ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
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ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
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farg1.d = float128_to_float64(ft0_128, &env->fp_status);
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}
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if (likely(!float64_is_any_nan(farg1.d))) {
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farg1.d = float64_chs(farg1.d);
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}
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}
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return farg1.ll;
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}
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/* fnmsub - fnmsub. */
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uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
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uint64_t arg3)
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{
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CPU_DoubleU farg1, farg2, farg3;
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farg1.ll = arg1;
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farg2.ll = arg2;
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farg3.ll = arg3;
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if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
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(float64_is_zero(farg1.d) &&
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float64_is_infinity(farg2.d)))) {
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/* Multiplication of zero by infinity */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
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} else {
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if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
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float64_is_signaling_nan(farg2.d, &env->fp_status) ||
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float64_is_signaling_nan(farg3.d, &env->fp_status))) {
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/* sNaN operation */
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float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
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}
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/* This is the way the PowerPC specification defines it */
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float128 ft0_128, ft1_128;
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ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
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ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
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ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
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if (unlikely(float128_is_infinity(ft0_128) &&
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float64_is_infinity(farg3.d) &&
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float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
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/* Magnitude subtraction of infinities */
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farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
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} else {
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ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
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ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
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farg1.d = float128_to_float64(ft0_128, &env->fp_status);
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}
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if (likely(!float64_is_any_nan(farg1.d))) {
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farg1.d = float64_chs(farg1.d);
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}
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}
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return farg1.ll;
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}
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FPU_FMADD(fmadd, MADD_FLGS)
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FPU_FMADD(fnmadd, NMADD_FLGS)
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FPU_FMADD(fmsub, MSUB_FLGS)
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FPU_FMADD(fnmsub, NMSUB_FLGS)
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/* frsp - frsp. */
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uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
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@ -2384,11 +2268,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
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float_check_status(env); \
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}
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#define MADD_FLGS 0
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#define MSUB_FLGS float_muladd_negate_c
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#define NMADD_FLGS float_muladd_negate_result
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#define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
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VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
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VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
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VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
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