target/arm: Fill in the WnR syndrome bit in mte_check_fail
According to AArch64.TagCheckFault, none of the other ISS values are provided, so we do not need to go so far as merge_syn_data_abort. But we were missing the WnR bit. Tested-by: Andrey Konovalov <andreyknvl@google.com> Reported-by: Andrey Konovalov <andreyknvl@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -519,7 +519,7 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
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{
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{
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int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
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int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
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ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
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ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
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int el, reg_el, tcf, select;
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int el, reg_el, tcf, select, is_write, syn;
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uint64_t sctlr;
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uint64_t sctlr;
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reg_el = regime_el(env, arm_mmu_idx);
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reg_el = regime_el(env, arm_mmu_idx);
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@ -547,9 +547,10 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
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*/
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*/
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cpu_restore_state(env_cpu(env), ra, true);
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cpu_restore_state(env_cpu(env), ra, true);
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env->exception.vaddress = dirty_ptr;
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env->exception.vaddress = dirty_ptr;
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raise_exception(env, EXCP_DATA_ABORT,
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syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11),
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is_write = FIELD_EX32(desc, MTEDESC, WRITE);
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exception_target_el(env));
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syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
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raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
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/* noreturn, but fall through to the assert anyway */
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/* noreturn, but fall through to the assert anyway */
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case 0:
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case 0:
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