Sparc32: reserve addresses for unimplemented devices on SS-20
Use empty_slot to reserve addresses for several unimplemented devices so they won't fault. - BPP (parallel port), DBRI (audio), SX (pixel processor), and vsimms (framebuffer) OBP for SS-20 either assumes these devices exist or probes without expecting faults. Signed-off-by: Bob Breuer <breuerr@mc.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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hw/sun4m.c
53
hw/sun4m.c
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@ -89,6 +89,7 @@
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#define MAX_CPUS 16
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#define MAX_CPUS 16
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#define MAX_PILS 16
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#define MAX_PILS 16
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#define MAX_VSIMMS 4
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#define ESCC_CLOCK 4915200
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#define ESCC_CLOCK 4915200
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@ -98,6 +99,10 @@ struct sun4m_hwdef {
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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target_phys_addr_t bpp_base, dbri_base, sx_base;
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struct {
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target_phys_addr_t reg_base, vram_base;
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} vsimm[MAX_VSIMMS];
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target_phys_addr_t ecc_base;
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target_phys_addr_t ecc_base;
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uint32_t ecc_version;
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uint32_t ecc_version;
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uint8_t nvram_machine_id;
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uint8_t nvram_machine_id;
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@ -810,6 +815,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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unsigned long kernel_size;
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unsigned long kernel_size;
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DriveInfo *fd[MAX_FD];
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DriveInfo *fd[MAX_FD];
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void *fw_cfg;
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void *fw_cfg;
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unsigned int num_vsimms;
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/* init CPUs */
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/* init CPUs */
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if (!cpu_model)
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if (!cpu_model)
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@ -872,8 +878,22 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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exit (1);
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}
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}
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tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
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num_vsimms = 0;
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graphic_depth);
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if (num_vsimms == 0) {
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tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
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graphic_depth);
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}
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for (i = num_vsimms; i < MAX_VSIMMS; i++) {
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/* vsimm registers probed by OBP */
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if (hwdef->vsimm[i].reg_base) {
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empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
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}
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}
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if (hwdef->sx_base) {
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empty_slot_init(hwdef->sx_base, 0x2000);
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}
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
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@ -920,6 +940,19 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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slavio_irq[5]);
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slavio_irq[5]);
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}
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}
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if (hwdef->dbri_base) {
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/* ISDN chip with attached CS4215 audio codec */
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/* prom space */
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empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
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/* reg space */
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empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
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}
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if (hwdef->bpp_base) {
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/* parallel port */
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empty_slot_init(hwdef->bpp_base, 0x20);
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}
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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RAM_size);
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@ -1063,9 +1096,25 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.dma_base = 0xef0400000ULL,
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.dma_base = 0xef0400000ULL,
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.esp_base = 0xef0800000ULL,
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.esp_base = 0xef0800000ULL,
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.le_base = 0xef0c00000ULL,
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.le_base = 0xef0c00000ULL,
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.bpp_base = 0xef4800000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.aux1_base = 0xff1800000ULL,
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.aux1_base = 0xff1800000ULL,
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.aux2_base = 0xff1a01000ULL,
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.aux2_base = 0xff1a01000ULL,
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.dbri_base = 0xee0000000ULL,
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.sx_base = 0xf80000000ULL,
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.vsimm = {
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{
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.reg_base = 0x9c000000ULL,
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.vram_base = 0xfc000000ULL
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}, {
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.reg_base = 0x90000000ULL,
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.vram_base = 0xf0000000ULL
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}, {
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.reg_base = 0x94000000ULL
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}, {
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.reg_base = 0x98000000ULL
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}
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},
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.ecc_base = 0xf00000000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x20000000, // version 0, implementation 2
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.ecc_version = 0x20000000, // version 0, implementation 2
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.nvram_machine_id = 0x72,
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.nvram_machine_id = 0x72,
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