target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. This is done by adding a field in hflags for MT bit, and adding functions check_mt() and check_cp0_mt(). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
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@ -1927,6 +1927,36 @@ static inline void check_xnp(DisasContext *ctx)
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}
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}
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}
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}
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/*
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* This code generates a "reserved instruction" exception if the
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* Config3 MT bit is NOT set.
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*/
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static inline void check_mt(DisasContext *ctx)
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{
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if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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#ifndef CONFIG_USER_ONLY
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/*
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* This code generates a "coprocessor unusable" exception if CP0 is not
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* available, and, if that is not the case, generates a "reserved instruction"
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* exception if the Config5 MT bit is NOT set. This is needed for availability
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* control of some of MT ASE instructions.
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*/
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static inline void check_cp0_mt(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
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generate_exception_err(ctx, EXCP_CpU, 0);
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} else {
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if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
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generate_exception_err(ctx, EXCP_RI, 0);
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}
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}
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}
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#endif
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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calling interface for 32 and 64-bit FPRs. No sense in changing
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@ -8595,7 +8625,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
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opn = "mthc0";
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opn = "mthc0";
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break;
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break;
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case OPC_MFTR:
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case OPC_MFTR:
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check_insn(ctx, ASE_MT);
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check_cp0_enabled(ctx);
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if (rd == 0) {
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if (rd == 0) {
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/* Treat as NOP. */
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/* Treat as NOP. */
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return;
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return;
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@ -8605,7 +8635,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
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opn = "mftr";
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opn = "mftr";
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break;
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break;
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case OPC_MTTR:
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case OPC_MTTR:
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check_insn(ctx, ASE_MT);
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check_cp0_enabled(ctx);
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gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
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gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
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ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
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ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
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opn = "mttr";
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opn = "mttr";
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@ -21962,7 +21992,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
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gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
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gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
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break;
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break;
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case OPC_FORK:
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case OPC_FORK:
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check_insn(ctx, ASE_MT);
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check_mt(ctx);
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{
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{
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TCGv t0 = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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@ -21975,7 +22005,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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break;
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break;
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case OPC_YIELD:
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case OPC_YIELD:
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check_insn(ctx, ASE_MT);
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check_mt(ctx);
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{
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{
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TCGv t0 = tcg_temp_new();
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TCGv t0 = tcg_temp_new();
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@ -23272,22 +23302,22 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
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op2 = MASK_MFMC0(ctx->opcode);
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op2 = MASK_MFMC0(ctx->opcode);
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switch (op2) {
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switch (op2) {
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case OPC_DMT:
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case OPC_DMT:
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check_insn(ctx, ASE_MT);
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check_cp0_mt(ctx);
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gen_helper_dmt(t0);
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gen_helper_dmt(t0);
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gen_store_gpr(t0, rt);
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gen_store_gpr(t0, rt);
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break;
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break;
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case OPC_EMT:
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case OPC_EMT:
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check_insn(ctx, ASE_MT);
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check_cp0_mt(ctx);
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gen_helper_emt(t0);
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gen_helper_emt(t0);
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gen_store_gpr(t0, rt);
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gen_store_gpr(t0, rt);
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break;
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break;
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case OPC_DVPE:
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case OPC_DVPE:
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check_insn(ctx, ASE_MT);
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check_cp0_mt(ctx);
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gen_helper_dvpe(t0, cpu_env);
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gen_helper_dvpe(t0, cpu_env);
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gen_store_gpr(t0, rt);
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gen_store_gpr(t0, rt);
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break;
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break;
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case OPC_EVPE:
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case OPC_EVPE:
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check_insn(ctx, ASE_MT);
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check_cp0_mt(ctx);
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gen_helper_evpe(t0, cpu_env);
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gen_helper_evpe(t0, cpu_env);
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gen_store_gpr(t0, rt);
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gen_store_gpr(t0, rt);
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break;
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break;
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