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@ -1110,6 +1110,8 @@ void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
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}
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#endif
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#define XO(X) offsetof(X86XSaveArea, X)
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static void do_xsave_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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int fpus, fptag, i;
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@ -1120,17 +1122,18 @@ static void do_xsave_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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for (i = 0; i < 8; i++) {
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fptag |= (env->fptags[i] << i);
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}
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cpu_stw_data_ra(env, ptr, env->fpuc, ra);
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cpu_stw_data_ra(env, ptr + 2, fpus, ra);
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cpu_stw_data_ra(env, ptr + 4, fptag ^ 0xff, ra);
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cpu_stw_data_ra(env, ptr + XO(legacy.fcw), env->fpuc, ra);
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cpu_stw_data_ra(env, ptr + XO(legacy.fsw), fpus, ra);
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cpu_stw_data_ra(env, ptr + XO(legacy.ftw), fptag ^ 0xff, ra);
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/* In 32-bit mode this is eip, sel, dp, sel.
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In 64-bit mode this is rip, rdp.
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But in either case we don't write actual data, just zeros. */
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cpu_stq_data_ra(env, ptr + 0x08, 0, ra); /* eip+sel; rip */
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cpu_stq_data_ra(env, ptr + 0x10, 0, ra); /* edp+sel; rdp */
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cpu_stq_data_ra(env, ptr + XO(legacy.fpip), 0, ra); /* eip+sel; rip */
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cpu_stq_data_ra(env, ptr + XO(legacy.fpdp), 0, ra); /* edp+sel; rdp */
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addr = ptr + 0x20;
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addr = ptr + XO(legacy.fpregs);
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for (i = 0; i < 8; i++) {
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floatx80 tmp = ST(i);
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helper_fstt(env, tmp, addr, ra);
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@ -1140,8 +1143,8 @@ static void do_xsave_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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static void do_xsave_mxcsr(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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cpu_stl_data_ra(env, ptr + 0x18, env->mxcsr, ra); /* mxcsr */
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cpu_stl_data_ra(env, ptr + 0x1c, 0x0000ffff, ra); /* mxcsr_mask */
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cpu_stl_data_ra(env, ptr + XO(legacy.mxcsr), env->mxcsr, ra);
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cpu_stl_data_ra(env, ptr + XO(legacy.mxcsr_mask), 0x0000ffff, ra);
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}
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static void do_xsave_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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@ -1155,7 +1158,7 @@ static void do_xsave_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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nb_xmm_regs = 8;
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}
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addr = ptr + 0xa0;
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addr = ptr + XO(legacy.xmm_regs);
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for (i = 0; i < nb_xmm_regs; i++) {
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cpu_stq_data_ra(env, addr, env->xmm_regs[i].ZMM_Q(0), ra);
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cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].ZMM_Q(1), ra);
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@ -1163,8 +1166,9 @@ static void do_xsave_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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}
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}
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static void do_xsave_bndregs(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xsave_bndregs(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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target_ulong addr = ptr + offsetof(XSaveBNDREG, bnd_regs);
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int i;
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for (i = 0; i < 4; i++, addr += 16) {
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@ -1173,15 +1177,17 @@ static void do_xsave_bndregs(CPUX86State *env, target_ulong addr, uintptr_t ra)
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}
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}
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static void do_xsave_bndcsr(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xsave_bndcsr(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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cpu_stq_data_ra(env, addr, env->bndcs_regs.cfgu, ra);
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cpu_stq_data_ra(env, addr + 8, env->bndcs_regs.sts, ra);
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cpu_stq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.cfgu),
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env->bndcs_regs.cfgu, ra);
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cpu_stq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.sts),
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env->bndcs_regs.sts, ra);
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}
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static void do_xsave_pkru(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xsave_pkru(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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cpu_stq_data_ra(env, addr, env->pkru, ra);
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cpu_stq_data_ra(env, ptr, env->pkru, ra);
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}
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void helper_fxsave(CPUX86State *env, target_ulong ptr)
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@ -1250,22 +1256,19 @@ static void do_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm,
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do_xsave_sse(env, ptr, ra);
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}
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if (opt & XSTATE_BNDREGS_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_BNDREGS_BIT].offset;
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do_xsave_bndregs(env, ptr + off, ra);
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do_xsave_bndregs(env, ptr + XO(bndreg_state), ra);
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}
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if (opt & XSTATE_BNDCSR_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_BNDCSR_BIT].offset;
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do_xsave_bndcsr(env, ptr + off, ra);
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do_xsave_bndcsr(env, ptr + XO(bndcsr_state), ra);
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}
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if (opt & XSTATE_PKRU_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_PKRU_BIT].offset;
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do_xsave_pkru(env, ptr + off, ra);
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do_xsave_pkru(env, ptr + XO(pkru_state), ra);
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}
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/* Update the XSTATE_BV field. */
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old_bv = cpu_ldq_data_ra(env, ptr + 512, ra);
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old_bv = cpu_ldq_data_ra(env, ptr + XO(header.xstate_bv), ra);
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new_bv = (old_bv & ~rfbm) | (inuse & rfbm);
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cpu_stq_data_ra(env, ptr + 512, new_bv, ra);
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cpu_stq_data_ra(env, ptr + XO(header.xstate_bv), new_bv, ra);
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}
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void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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@ -1281,12 +1284,13 @@ void helper_xsaveopt(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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int i, fpus, fptag;
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int i, fpuc, fpus, fptag;
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target_ulong addr;
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cpu_set_fpuc(env, cpu_lduw_data_ra(env, ptr, ra));
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fpus = cpu_lduw_data_ra(env, ptr + 2, ra);
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fptag = cpu_lduw_data_ra(env, ptr + 4, ra);
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fpuc = cpu_lduw_data_ra(env, ptr + XO(legacy.fcw), ra);
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fpus = cpu_lduw_data_ra(env, ptr + XO(legacy.fsw), ra);
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fptag = cpu_lduw_data_ra(env, ptr + XO(legacy.ftw), ra);
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cpu_set_fpuc(env, fpuc);
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env->fpstt = (fpus >> 11) & 7;
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env->fpus = fpus & ~0x3800;
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fptag ^= 0xff;
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@ -1294,7 +1298,7 @@ static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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env->fptags[i] = ((fptag >> i) & 1);
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}
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addr = ptr + 0x20;
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addr = ptr + XO(legacy.fpregs);
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for (i = 0; i < 8; i++) {
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floatx80 tmp = helper_fldt(env, addr, ra);
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ST(i) = tmp;
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@ -1304,7 +1308,7 @@ static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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static void do_xrstor_mxcsr(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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cpu_set_mxcsr(env, cpu_ldl_data_ra(env, ptr + 0x18, ra));
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cpu_set_mxcsr(env, cpu_ldl_data_ra(env, ptr + XO(legacy.mxcsr), ra));
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}
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static void do_xrstor_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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@ -1318,7 +1322,7 @@ static void do_xrstor_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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nb_xmm_regs = 8;
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}
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addr = ptr + 0xa0;
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addr = ptr + XO(legacy.xmm_regs);
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for (i = 0; i < nb_xmm_regs; i++) {
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env->xmm_regs[i].ZMM_Q(0) = cpu_ldq_data_ra(env, addr, ra);
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env->xmm_regs[i].ZMM_Q(1) = cpu_ldq_data_ra(env, addr + 8, ra);
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@ -1326,8 +1330,9 @@ static void do_xrstor_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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}
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}
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static void do_xrstor_bndregs(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xrstor_bndregs(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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target_ulong addr = ptr + offsetof(XSaveBNDREG, bnd_regs);
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int i;
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for (i = 0; i < 4; i++, addr += 16) {
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@ -1336,16 +1341,18 @@ static void do_xrstor_bndregs(CPUX86State *env, target_ulong addr, uintptr_t ra)
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}
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}
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static void do_xrstor_bndcsr(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xrstor_bndcsr(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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/* FIXME: Extend highest implemented bit of linear address. */
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env->bndcs_regs.cfgu = cpu_ldq_data_ra(env, addr, ra);
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env->bndcs_regs.sts = cpu_ldq_data_ra(env, addr + 8, ra);
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env->bndcs_regs.cfgu
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= cpu_ldq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.cfgu), ra);
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env->bndcs_regs.sts
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= cpu_ldq_data_ra(env, ptr + offsetof(XSaveBNDCSR, bndcsr.sts), ra);
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}
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static void do_xrstor_pkru(CPUX86State *env, target_ulong addr, uintptr_t ra)
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static void do_xrstor_pkru(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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env->pkru = cpu_ldq_data_ra(env, addr, ra);
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env->pkru = cpu_ldq_data_ra(env, ptr, ra);
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}
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void helper_fxrstor(CPUX86State *env, target_ulong ptr)
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@ -1373,7 +1380,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr)
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void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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{
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uintptr_t ra = GETPC();
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uint64_t xstate_bv, xcomp_bv0, xcomp_bv1;
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uint64_t xstate_bv, xcomp_bv, reserve0;
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rfbm &= env->xcr0;
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@ -1387,7 +1394,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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raise_exception_ra(env, EXCP0D_GPF, ra);
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}
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xstate_bv = cpu_ldq_data_ra(env, ptr + 512, ra);
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xstate_bv = cpu_ldq_data_ra(env, ptr + XO(header.xstate_bv), ra);
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if ((int64_t)xstate_bv < 0) {
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/* FIXME: Compact form. */
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@ -1396,15 +1403,19 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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/* Standard form. */
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/* The XSTATE field must not set bits not present in XCR0. */
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/* The XSTATE_BV field must not set bits not present in XCR0. */
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if (xstate_bv & ~env->xcr0) {
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raise_exception_ra(env, EXCP0D_GPF, ra);
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}
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/* The XCOMP field must be zero. */
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xcomp_bv0 = cpu_ldq_data_ra(env, ptr + 520, ra);
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xcomp_bv1 = cpu_ldq_data_ra(env, ptr + 528, ra);
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if (xcomp_bv0 || xcomp_bv1) {
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/* The XCOMP_BV field must be zero. Note that, as of the April 2016
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|
revision, the description of the XSAVE Header (Vol 1, Sec 13.4.2)
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describes only XCOMP_BV, but the description of the standard form
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|
|
of XRSTOR (Vol 1, Sec 13.8.1) checks bytes 23:8 for zero, which
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includes the next 64-bit field. */
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xcomp_bv = cpu_ldq_data_ra(env, ptr + XO(header.xcomp_bv), ra);
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reserve0 = cpu_ldq_data_ra(env, ptr + XO(header.reserve0), ra);
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if (xcomp_bv || reserve0) {
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raise_exception_ra(env, EXCP0D_GPF, ra);
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}
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@ -1430,8 +1441,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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}
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if (rfbm & XSTATE_BNDREGS_MASK) {
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if (xstate_bv & XSTATE_BNDREGS_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_BNDREGS_BIT].offset;
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|
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do_xrstor_bndregs(env, ptr + off, ra);
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do_xrstor_bndregs(env, ptr + XO(bndreg_state), ra);
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|
env->hflags |= HF_MPX_IU_MASK;
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} else {
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|
|
memset(env->bnd_regs, 0, sizeof(env->bnd_regs));
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|
|
@ -1440,8 +1450,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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}
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|
|
if (rfbm & XSTATE_BNDCSR_MASK) {
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if (xstate_bv & XSTATE_BNDCSR_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_BNDCSR_BIT].offset;
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do_xrstor_bndcsr(env, ptr + off, ra);
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do_xrstor_bndcsr(env, ptr + XO(bndcsr_state), ra);
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} else {
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memset(&env->bndcs_regs, 0, sizeof(env->bndcs_regs));
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}
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@ -1450,8 +1459,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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if (rfbm & XSTATE_PKRU_MASK) {
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uint64_t old_pkru = env->pkru;
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if (xstate_bv & XSTATE_PKRU_MASK) {
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target_ulong off = x86_ext_save_areas[XSTATE_PKRU_BIT].offset;
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do_xrstor_pkru(env, ptr + off, ra);
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do_xrstor_pkru(env, ptr + XO(pkru_state), ra);
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} else {
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env->pkru = 0;
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}
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@ -1462,6 +1470,8 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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}
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}
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#undef XO
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uint64_t helper_xgetbv(CPUX86State *env, uint32_t ecx)
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{
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/* The OS must have enabled XSAVE. */
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