tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
d5dd696fe3
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9b9c37c364
40
configure
vendored
40
configure
vendored
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@ -111,7 +111,6 @@ source_path=`dirname "$0"`
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cpu=""
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interp_prefix="/usr/gnemul/qemu-%M"
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static="no"
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sparc_cpu=""
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cross_prefix=""
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audio_drv_list=""
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audio_card_list="ac97 es1370 sb16 hda"
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@ -241,21 +240,6 @@ for opt do
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;;
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--disable-debug-info) debug_info="no"
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;;
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--sparc_cpu=*)
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sparc_cpu="$optarg"
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case $sparc_cpu in
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v7|v8|v8plus|v8plusa)
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cpu="sparc"
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;;
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v9)
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cpu="sparc64"
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;;
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*)
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echo "undefined SPARC architecture. Exiting";
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exit 1
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;;
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esac
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;;
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esac
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done
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# OS specific
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@ -343,8 +327,6 @@ elif check_define __i386__ ; then
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elif check_define __x86_64__ ; then
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cpu="x86_64"
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elif check_define __sparc__ ; then
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# We can't check for 64 bit (when gcc is biarch) or V8PLUSA
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# They must be specified using --sparc_cpu
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if check_define __arch64__ ; then
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cpu="sparc64"
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else
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@ -792,8 +774,6 @@ for opt do
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;;
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--enable-uname-release=*) uname_release="$optarg"
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;;
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--sparc_cpu=*)
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;;
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--enable-werror) werror="yes"
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;;
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--disable-werror) werror="no"
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@ -881,31 +861,19 @@ for opt do
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esac
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done
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#
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# If cpu ~= sparc and sparc_cpu hasn't been defined, plug in the right
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# QEMU_CFLAGS/LDFLAGS (assume sparc_v8plus for 32-bit and sparc_v9 for 64-bit)
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#
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host_guest_base="no"
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case "$cpu" in
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sparc) case $sparc_cpu in
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v7|v8)
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QEMU_CFLAGS="-mcpu=${sparc_cpu} -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS"
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;;
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v8plus|v8plusa)
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QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS"
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;;
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*) # sparc_cpu not defined in the command line
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QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_v8plus__ $QEMU_CFLAGS"
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esac
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sparc)
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LDFLAGS="-m32 $LDFLAGS"
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QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
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QEMU_CFLAGS="-m32 -mcpu=ultrasparc $QEMU_CFLAGS"
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QEMU_CFLAGS="-ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
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if test "$solaris" = "no" ; then
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QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
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fi
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;;
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sparc64)
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QEMU_CFLAGS="-m64 -mcpu=ultrasparc -D__sparc_v9__ $QEMU_CFLAGS"
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LDFLAGS="-m64 $LDFLAGS"
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QEMU_CFLAGS="-m64 -mcpu=ultrasparc $QEMU_CFLAGS"
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QEMU_CFLAGS="-ffixed-g5 -ffixed-g6 -ffixed-g7 $QEMU_CFLAGS"
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if test "$solaris" != "no" ; then
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QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS"
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2
disas.c
2
disas.c
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@ -316,9 +316,7 @@ void disas(FILE *out, void *code, unsigned long size)
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print_insn = print_insn_alpha;
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#elif defined(__sparc__)
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print_insn = print_insn_sparc;
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#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
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disasm_info.mach = bfd_mach_sparc_v9b;
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#endif
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#elif defined(__arm__)
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print_insn = print_insn_arm;
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#elif defined(__MIPSEB__)
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6
exec.c
6
exec.c
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@ -86,7 +86,7 @@ static int nb_tbs;
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/* any access to the tbs or the page table must use this lock */
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spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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#if defined(__arm__) || defined(__sparc_v9__)
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#if defined(__arm__) || defined(__sparc__)
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/* The prologue must be reachable with a direct jump. ARM and Sparc64
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have limited branch ranges (possibly also PPC) so place it in a
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section close to code segment. */
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@ -541,7 +541,7 @@ static void code_gen_alloc(unsigned long tb_size)
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/* Cannot map more than that */
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if (code_gen_buffer_size > (800 * 1024 * 1024))
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code_gen_buffer_size = (800 * 1024 * 1024);
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#elif defined(__sparc_v9__)
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#elif defined(__sparc__) && HOST_LONG_BITS == 64
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// Map the buffer below 2G, so we can use direct calls and branches
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start = (void *) 0x40000000UL;
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if (code_gen_buffer_size > (512 * 1024 * 1024))
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@ -581,7 +581,7 @@ static void code_gen_alloc(unsigned long tb_size)
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/* Cannot map more than that */
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if (code_gen_buffer_size > (800 * 1024 * 1024))
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code_gen_buffer_size = (800 * 1024 * 1024);
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#elif defined(__sparc_v9__)
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#elif defined(__sparc__) && HOST_LONG_BITS == 64
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// Map the buffer below 2G, so we can use direct calls and branches
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addr = (void *) 0x40000000UL;
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if (code_gen_buffer_size > (512 * 1024 * 1024)) {
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@ -218,7 +218,7 @@ static inline int64_t cpu_get_real_ticks(void)
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return val;
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}
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#elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
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#elif defined(__sparc__)
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static inline int64_t cpu_get_real_ticks (void)
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{
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@ -227,6 +227,8 @@ static inline int64_t cpu_get_real_ticks (void)
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asm volatile("rd %%tick,%0" : "=r"(rval));
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return rval;
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#else
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/* We need an %o or %g register for this. For recent enough gcc
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there is an "h" constraint for that. Don't bother with that. */
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union {
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uint64_t i64;
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struct {
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@ -234,8 +236,8 @@ static inline int64_t cpu_get_real_ticks (void)
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uint32_t low;
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} i32;
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} rval;
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asm volatile("rd %%tick,%1; srlx %1,32,%0"
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: "=r"(rval.i32.high), "=r"(rval.i32.low));
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asm volatile("rd %%tick,%%g1; srlx %%g1,32,%0; mov %%g1,%1"
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: "=r"(rval.i32.high), "=r"(rval.i32.low) : : "g1");
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return rval.i64;
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#endif
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}
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@ -621,18 +621,10 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
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default:
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tcg_out_cmp(s, c1, c2, c2const);
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#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out32(s, ARITH_MOVCC | INSN_RD(ret)
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| INSN_RS1(tcg_cond_to_bcond[cond])
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| MOVCC_ICC | INSN_IMM11(1));
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#else
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t = gen_new_label();
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tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
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tcg_out_movi_imm13(s, ret, 1);
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tcg_out_movi_imm13(s, ret, 0);
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tcg_out_label(s, t, s->code_ptr);
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#endif
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return;
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}
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@ -742,7 +734,7 @@ static const void * const qemu_st_helpers[4] = {
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#endif
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#endif
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#ifdef __arch64__
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#if TCG_TARGET_REG_BITS == 64
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#define HOST_LD_OP LDX
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#define HOST_ST_OP STX
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#define HOST_SLL_OP SHIFT_SLLX
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#if TCG_TARGET_REG_BITS == 64
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# define ELF_HOST_MACHINE EM_SPARCV9
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#elif defined(__sparc_v8plus__)
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#else
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# define ELF_HOST_MACHINE EM_SPARC32PLUS
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# define ELF_HOST_FLAGS EF_SPARC_32PLUS
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#else
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# define ELF_HOST_MACHINE EM_SPARC
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#endif
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typedef struct {
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@ -67,7 +67,8 @@ typedef enum {
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_I6
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#ifdef __arch64__
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#if TCG_TARGET_REG_BITS == 64
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// Reserve space for AREG0
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#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
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TCG_STATIC_CALL_ARGS_SIZE)
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#define TCG_TARGET_STACK_ALIGN 8
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#endif
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#ifdef __arch64__
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_EXTEND_ARGS 1
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#endif
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#ifdef CONFIG_SOLARIS
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#define TCG_AREG0 TCG_REG_G2
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#elif defined(__sparc_v9__)
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#elif HOST_LONG_BITS == 64
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#define TCG_AREG0 TCG_REG_G5
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#else
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#define TCG_AREG0 TCG_REG_G6
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@ -1457,7 +1457,8 @@ static void temp_allocate_frame(TCGContext *s, int temp)
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{
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TCGTemp *ts;
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ts = &s->temps[temp];
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#ifndef __sparc_v9__ /* Sparc64 stack is accessed with offset of 2047 */
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#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
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/* Sparc64 stack is accessed with offset of 2047 */
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s->current_frame_offset = (s->current_frame_offset +
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(tcg_target_long)sizeof(tcg_target_long) - 1) &
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~(sizeof(tcg_target_long) - 1);
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