hw/timer/armv7m_systick: Forbid non-privileged accesses
Like most of the v7M memory mapped system registers, the systick registers are accessible to privileged code only and user accesses must generate a BusFault. We implement that for registers in the NVIC proper already, but missed it for systick since we implement it as a separate device. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190617175317.27557-6-peter.maydell@linaro.org
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@ -75,11 +75,17 @@ static void systick_timer_tick(void *opaque)
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}
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}
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}
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}
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static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
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static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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{
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SysTickState *s = opaque;
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SysTickState *s = opaque;
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uint32_t val;
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uint32_t val;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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switch (addr) {
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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case 0x0: /* SysTick Control and Status. */
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val = s->control;
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val = s->control;
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@ -121,14 +127,21 @@ static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
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}
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}
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trace_systick_read(addr, val, size);
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trace_systick_read(addr, val, size);
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return val;
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*data = val;
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return MEMTX_OK;
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}
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}
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static void systick_write(void *opaque, hwaddr addr,
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static MemTxResult systick_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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{
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SysTickState *s = opaque;
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SysTickState *s = opaque;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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trace_systick_write(addr, value, size);
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trace_systick_write(addr, value, size);
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switch (addr) {
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switch (addr) {
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@ -172,11 +185,12 @@ static void systick_write(void *opaque, hwaddr addr,
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
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"SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
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}
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}
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return MEMTX_OK;
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}
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}
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static const MemoryRegionOps systick_ops = {
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static const MemoryRegionOps systick_ops = {
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.read = systick_read,
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.read_with_attrs = systick_read,
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.write = systick_write,
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.write_with_attrs = systick_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.max_access_size = 4,
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