hw: arm_gic: Introduce gic_set_priority function
To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -168,6 +168,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
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return new_irq;
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}
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void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val)
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{
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if (irq < GIC_INTERNAL) {
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s->priority1[irq][cpu] = val;
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} else {
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s->priority2[(irq) - GIC_INTERNAL] = val;
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}
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}
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void gic_complete_irq(GICState *s, int cpu, int irq)
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{
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int update = 0;
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@ -443,11 +452,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_INTERNAL) {
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s->priority1[irq][cpu] = value;
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} else {
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s->priority2[irq - GIC_INTERNAL] = value;
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}
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gic_set_priority(s, cpu, irq, value);
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
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* annoying exception of the 11MPCore's GIC.
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@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu);
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void gic_complete_irq(GICState *s, int cpu, int irq);
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void gic_update(GICState *s);
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void gic_init_irqs_and_distributor(GICState *s, int num_irq);
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void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val);
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#endif /* !QEMU_ARM_GIC_INTERNAL_H */
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