target/mips: realign comments to fix checkpatch warnings
Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
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@ -37,7 +37,8 @@ union fpr_t {
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/* FPU/MSA register mapping is not tested on big-endian hosts. */
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wr_t wr; /* vector data */
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};
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/* define FP_ENDIAN_IDX to access the same location
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/*
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*define FP_ENDIAN_IDX to access the same location
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* in the fpr_t union regardless of the host endianness
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*/
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#if defined(HOST_WORDS_BIGENDIAN)
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@ -976,9 +977,11 @@ struct CPUMIPSState {
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x1F5807FF
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
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the bits as the value of mmu_idx. */
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/*
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* The KSU flags must be the lowest bits in hflags. The flag order
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* must be the same as defined for CP0 Status. This allows to use
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* the bits as the value of mmu_idx.
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*/
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#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
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#define MIPS_HFLAG_UM 0x00002 /* user mode flag */
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#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
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@ -988,18 +991,22 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
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#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
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#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
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/* True if the MIPS IV COP1X instructions can be used. This also
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controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
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and RSQRT.D. */
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/*
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* True if the MIPS IV COP1X instructions can be used. This also
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* controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
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* and RSQRT.D.
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*/
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#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
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#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
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#define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
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#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
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#define MIPS_HFLAG_M16_SHIFT 10
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/* If translation is interrupted between the branch instruction and
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/*
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* If translation is interrupted between the branch instruction and
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* the delay slot, record what type of branch it is so that we can
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* resume translation properly. It might be possible to reduce
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* this from three bits to two. */
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* this from three bits to two.
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*/
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#define MIPS_HFLAG_BMASK_BASE 0x803800
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#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
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@ -1086,8 +1093,10 @@ void mips_cpu_list(void);
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extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
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extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
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/* MMU modes definitions. We carefully match the indices with our
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hflags layout. */
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/*
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* MMU modes definitions. We carefully match the indices with our
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* hflags layout.
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*/
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _super
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#define MMU_MODE2_SUFFIX _user
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@ -1110,7 +1119,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
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#include "exec/cpu-all.h"
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/* Memory access type :
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/*
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* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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