haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

tcg/loongarch64: Implement setcond ops

Browse source 
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-21-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
WANG Xuerui 2021-12-21 13:40:54 +08:00 committed by Richard Henderson
parent 94505c02f4
commit 9ee775cf29
2 changed files with 70 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
tcg/loongarch64/tcg-target-con-set.h
View file

@ -22,6 +22,7 @@ C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
C_O1_I2(r, rZ, rZ)

69
tcg/loongarch64/tcg-target.c.inc
View file

@ -434,6 +434,66 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
}
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGReg arg1, TCGReg arg2, bool c2)
{
TCGReg tmp;
if (c2) {
tcg_debug_assert(arg2 == 0);
}
switch (cond) {
case TCG_COND_EQ:
if (c2) {
tmp = arg1;
} else {
tcg_out_opc_sub_d(s, ret, arg1, arg2);
tmp = ret;
}
tcg_out_opc_sltui(s, ret, tmp, 1);
break;
case TCG_COND_NE:
if (c2) {
tmp = arg1;
} else {
tcg_out_opc_sub_d(s, ret, arg1, arg2);
tmp = ret;
}
tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
break;
case TCG_COND_LT:
tcg_out_opc_slt(s, ret, arg1, arg2);
break;
case TCG_COND_GE:
tcg_out_opc_slt(s, ret, arg1, arg2);
tcg_out_opc_xori(s, ret, ret, 1);
break;
case TCG_COND_LE:
tcg_out_setcond(s, TCG_COND_GE, ret, arg2, arg1, false);
break;
case TCG_COND_GT:
tcg_out_setcond(s, TCG_COND_LT, ret, arg2, arg1, false);
break;
case TCG_COND_LTU:
tcg_out_opc_sltu(s, ret, arg1, arg2);
break;
case TCG_COND_GEU:
tcg_out_opc_sltu(s, ret, arg1, arg2);
tcg_out_opc_xori(s, ret, ret, 1);
break;
case TCG_COND_LEU:
tcg_out_setcond(s, TCG_COND_GEU, ret, arg2, arg1, false);
break;
case TCG_COND_GTU:
tcg_out_setcond(s, TCG_COND_LTU, ret, arg2, arg1, false);
break;
default:
g_assert_not_reached();
break;
}
}
/*
* Branch helpers
*/
@ -815,6 +875,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_mod_du(s, a0, a1, a2);
break;
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2, c2);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@ -901,6 +966,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_ctz_i64:
return C_O1_I2(r, r, rW);
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
return C_O1_I2(r, r, rZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
/* Must deposit into the same register as input */