microblaze: Add support for load/store reversed
Load/store reversed (lwr/swr) are insns that endian translate the sub-word part of the address and byteswap the data lanes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
This commit is contained in:
Edgar E. Iglesias
parent
9ef5535763
commit
9f8beb6636
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@ -817,12 +817,35 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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return t;
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}
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static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
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{
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if (size == 4) {
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tcg_gen_bswap32_tl(dst, src);
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} else if (size == 2) {
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TCGv t = tcg_temp_new();
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/* bswap16 assumes the high bits are zero. */
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tcg_gen_andi_tl(t, src, 0xffff);
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tcg_gen_bswap16_tl(dst, t);
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tcg_temp_free(t);
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} else {
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/* Ignore.
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cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
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*/
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}
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}
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static void dec_load(DisasContext *dc)
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{
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TCGv t, *addr;
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unsigned int size;
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unsigned int size, rev = 0;
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size = 1 << (dc->opcode & 3);
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if (!dc->type_b) {
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rev = (dc->ir >> 9) & 1;
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}
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
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@ -830,10 +853,63 @@ static void dec_load(DisasContext *dc)
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return;
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}
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LOG_DIS("l %x %d\n", dc->opcode, size);
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LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
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t_sync_flags(dc);
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addr = compute_ldst_addr(dc, &t);
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/*
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* When doing reverse accesses we need to do two things.
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*
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* 1. Reverse the address wrt endianess.
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* 2. Byteswap the data lanes on the way back into the CPU core.
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*/
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if (rev && size != 4) {
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/* Endian reverse the address. t is addr. */
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switch (size) {
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case 1:
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{
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/* 00 -> 11
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01 -> 10
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10 -> 10
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11 -> 00 */
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TCGv low = tcg_temp_new();
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/* Force addr into the temp. */
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if (addr != &t) {
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t = tcg_temp_new();
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tcg_gen_mov_tl(t, *addr);
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addr = &t;
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}
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tcg_gen_andi_tl(low, t, 3);
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tcg_gen_sub_tl(low, tcg_const_tl(3), low);
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tcg_gen_andi_tl(t, t, ~3);
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tcg_gen_or_tl(t, t, low);
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tcg_gen_mov_tl(env_debug, low);
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tcg_gen_mov_tl(env_imm, t);
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tcg_temp_free(low);
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break;
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}
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case 2:
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/* 00 -> 10
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10 -> 00. */
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/* Force addr into the temp. */
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if (addr != &t) {
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t = tcg_temp_new();
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tcg_gen_xori_tl(t, *addr, 2);
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addr = &t;
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} else {
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tcg_gen_xori_tl(t, t, 2);
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}
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break;
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default:
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cpu_abort(dc->env, "Invalid reverse size\n");
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break;
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}
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}
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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sync_jmpstate(dc);
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@ -852,13 +928,22 @@ static void dec_load(DisasContext *dc)
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
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gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
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tcg_const_tl(0), tcg_const_tl(size - 1));
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if (dc->rd)
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tcg_gen_mov_tl(cpu_R[dc->rd], v);
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if (dc->rd) {
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if (rev) {
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dec_byteswap(dc, cpu_R[dc->rd], v, size);
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} else {
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tcg_gen_mov_tl(cpu_R[dc->rd], v);
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}
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}
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tcg_temp_free(v);
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} else {
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if (dc->rd) {
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gen_load(dc, cpu_R[dc->rd], *addr, size);
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if (rev) {
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dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
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}
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} else {
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/* We are loading into r0, no need to reverse. */
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gen_load(dc, env_imm, *addr, size);
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}
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}
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@ -885,9 +970,12 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
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static void dec_store(DisasContext *dc)
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{
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TCGv t, *addr;
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unsigned int size;
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unsigned int size, rev = 0;
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size = 1 << (dc->opcode & 3);
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if (!dc->type_b) {
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rev = (dc->ir >> 9) & 1;
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}
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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@ -896,19 +984,84 @@ static void dec_store(DisasContext *dc)
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return;
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}
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LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
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LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
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t_sync_flags(dc);
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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sync_jmpstate(dc);
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addr = compute_ldst_addr(dc, &t);
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gen_store(dc, *addr, cpu_R[dc->rd], size);
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if (rev && size != 4) {
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/* Endian reverse the address. t is addr. */
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switch (size) {
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case 1:
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{
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/* 00 -> 11
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01 -> 10
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10 -> 10
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11 -> 00 */
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TCGv low = tcg_temp_new();
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/* Force addr into the temp. */
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if (addr != &t) {
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t = tcg_temp_new();
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tcg_gen_mov_tl(t, *addr);
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addr = &t;
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}
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tcg_gen_andi_tl(low, t, 3);
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tcg_gen_sub_tl(low, tcg_const_tl(3), low);
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tcg_gen_andi_tl(t, t, ~3);
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tcg_gen_or_tl(t, t, low);
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tcg_gen_mov_tl(env_debug, low);
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tcg_gen_mov_tl(env_imm, t);
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tcg_temp_free(low);
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break;
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}
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case 2:
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/* 00 -> 10
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10 -> 00. */
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/* Force addr into the temp. */
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if (addr != &t) {
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t = tcg_temp_new();
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tcg_gen_xori_tl(t, *addr, 2);
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addr = &t;
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} else {
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tcg_gen_xori_tl(t, t, 2);
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}
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break;
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default:
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cpu_abort(dc->env, "Invalid reverse size\n");
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break;
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}
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if (size != 1) {
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TCGv bs_data = tcg_temp_new();
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dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
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gen_store(dc, *addr, bs_data, size);
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tcg_temp_free(bs_data);
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} else {
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gen_store(dc, *addr, cpu_R[dc->rd], size);
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}
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} else {
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if (rev) {
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TCGv bs_data = tcg_temp_new();
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dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
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gen_store(dc, *addr, bs_data, size);
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tcg_temp_free(bs_data);
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} else {
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gen_store(dc, *addr, cpu_R[dc->rd], size);
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}
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}
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/* Verify alignment if needed. */
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if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
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/* FIXME: if the alignment is wrong, we should restore the value
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* in memory.
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* in memory. One possible way to acheive this is to probe
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* the MMU prior to the memaccess, thay way we could put
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* the alignment checks in between the probe and the mem
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* access.
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*/
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gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
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tcg_const_tl(1), tcg_const_tl(size - 1));
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