target/mips: Define a bit for MXU in insn_flags
Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
parent
eb5559f67d
commit
a031ac6161
|
@ -69,6 +69,7 @@
|
|||
* bits 56-63: vendor-specific ASEs
|
||||
*/
|
||||
#define ASE_MMI 0x0100000000000000ULL
|
||||
#define ASE_MXU 0x0200000000000000ULL
|
||||
|
||||
/* MIPS CPU defines. */
|
||||
#define CPU_MIPS1 (ISA_MIPS1)
|
||||
|
|
Loading…
Reference in a new issue