tcg-ppc64: Use TCGMemOp within qemu_ldst routines
Signed-off-by: Richard Henderson <rth@twiddle.net>
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f1a16dcdd5
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a058557381
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@ -809,22 +809,28 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
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}
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}
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static const uint32_t qemu_ldx_opc[8] = {
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#ifdef TARGET_WORDS_BIGENDIAN
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LBZX, LHZX, LWZX, LDX,
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0, LHAX, LWAX, LDX
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#else
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LBZX, LHBRX, LWBRX, LDBRX,
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0, 0, 0, LDBRX,
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#endif
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static const uint32_t qemu_ldx_opc[16] = {
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[MO_UB] = LBZX,
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[MO_UW] = LHZX,
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[MO_UL] = LWZX,
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[MO_Q] = LDX,
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[MO_SW] = LHAX,
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[MO_SL] = LWAX,
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[MO_BSWAP | MO_UB] = LBZX,
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[MO_BSWAP | MO_UW] = LHBRX,
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[MO_BSWAP | MO_UL] = LWBRX,
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[MO_BSWAP | MO_Q] = LDBRX,
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};
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static const uint32_t qemu_stx_opc[4] = {
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#ifdef TARGET_WORDS_BIGENDIAN
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STBX, STHX, STWX, STDX
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#else
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STBX, STHBRX, STWBRX, STDBRX,
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#endif
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static const uint32_t qemu_stx_opc[16] = {
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[MO_UB] = STBX,
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[MO_UW] = STHX,
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[MO_UL] = STWX,
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[MO_Q] = STDX,
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[MO_BSWAP | MO_UB] = STBX,
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[MO_BSWAP | MO_UW] = STHBRX,
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[MO_BSWAP | MO_UL] = STWBRX,
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[MO_BSWAP | MO_Q] = STDBRX,
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};
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static const uint32_t qemu_exts_opc[4] = {
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@ -856,7 +862,7 @@ static const void * const qemu_st_helpers[4] = {
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in CR7, loads the addend of the TLB into R3, and returns the register
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containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
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static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
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int mem_index, bool is_read)
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{
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int cmp_off
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@ -929,7 +935,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
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/* Record the context of a call to the out of line helper code for the slow
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path for a load or store, so that we can later generate the correct
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helper code. */
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld, int opc,
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
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int data_reg, int addr_reg, int mem_index,
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uint8_t *raddr, uint8_t *label_ptr)
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{
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@ -946,8 +952,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, int opc,
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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int opc = lb->opc;
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int s_bits = opc & 3;
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TCGMemOp opc = lb->opc & MO_SSIZE;
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TCGMemOp s_bits = lb->opc & MO_SIZE;
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reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
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@ -962,7 +968,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[s_bits], 1);
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if (opc & 4) {
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if (opc & MO_SIGN) {
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uint32_t insn = qemu_exts_opc[s_bits];
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tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
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} else {
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@ -974,7 +980,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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int opc = lb->opc;
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TCGMemOp s_bits = lb->opc & MO_SIZE;
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reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
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@ -985,20 +991,21 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
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tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
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0, 64 - (1 << (3 + opc)));
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0, 64 - (1 << (3 + s_bits)));
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
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tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
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tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
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tcg_out_call(s, (tcg_target_long)qemu_st_helpers[s_bits], 1);
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tcg_out_b(s, 0, (uintptr_t)lb->raddr);
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addr_reg, data_reg, rbase;
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uint32_t insn, s_bits;
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uint32_t insn;
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TCGMemOp s_bits = opc & MO_SIZE;
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#ifdef CONFIG_SOFTMMU
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int mem_index;
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void *label_ptr;
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@ -1006,7 +1013,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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data_reg = *args++;
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addr_reg = *args++;
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s_bits = opc & 3;
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#ifdef CONFIG_SOFTMMU
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mem_index = *args;
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@ -1035,7 +1041,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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} else if (insn) {
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tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
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} else {
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insn = qemu_ldx_opc[s_bits];
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insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
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tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
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insn = qemu_exts_opc[s_bits];
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tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
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@ -1047,7 +1053,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addr_reg, rbase, data_reg;
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uint32_t insn;
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@ -1062,7 +1068,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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#ifdef CONFIG_SOFTMMU
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mem_index = *args;
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addr_reg = tcg_out_tlb_read(s, opc, addr_reg, mem_index, false);
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addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
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/* Load a pointer into the current opcode w/conditional branch-link. */
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label_ptr = s->code_ptr;
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@ -1827,38 +1833,38 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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case INDEX_op_qemu_ld8u:
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tcg_out_qemu_ld(s, args, 0);
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tcg_out_qemu_ld(s, args, MO_UB);
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break;
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case INDEX_op_qemu_ld8s:
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tcg_out_qemu_ld(s, args, 0 | 4);
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tcg_out_qemu_ld(s, args, MO_SB);
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break;
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case INDEX_op_qemu_ld16u:
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tcg_out_qemu_ld(s, args, 1);
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tcg_out_qemu_ld(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_ld16s:
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tcg_out_qemu_ld(s, args, 1 | 4);
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tcg_out_qemu_ld(s, args, MO_TESW);
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break;
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case INDEX_op_qemu_ld32:
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case INDEX_op_qemu_ld32u:
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tcg_out_qemu_ld(s, args, 2);
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tcg_out_qemu_ld(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_ld32s:
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tcg_out_qemu_ld(s, args, 2 | 4);
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tcg_out_qemu_ld(s, args, MO_TESL);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, 3);
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tcg_out_qemu_ld(s, args, MO_TEQ);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, 0);
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tcg_out_qemu_st(s, args, MO_UB);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, args, 1);
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tcg_out_qemu_st(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, args, 2);
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tcg_out_qemu_st(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, args, 3);
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tcg_out_qemu_st(s, args, MO_TEQ);
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break;
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case INDEX_op_ext8s_i32:
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