target-ppc: Fix openpic timer read register offset
openpic_tmr_read() is incorrectly computing register offset of the TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer registers. Specifically the offset of timer registers for openpic_tmr_read() is not accounting for the timer frequency reporting register (TFFR) which is the first register in the "tmr" memory region. openpic_tmr_write() *is* correctly computing the offset by adding 0x10f0 to the address prior to computing the register index. This patch instead subtracts 0x10 in both the read and write routines and eliminates some other gratuitous differences between the functions. Signed-off-by: Aaron Larson <alarson@ddci.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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}
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static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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unsigned len)
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{
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OpenPICState *opp = opaque;
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int idx;
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addr += 0x10f0;
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DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
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__func__, addr, val);
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__func__, (addr + 0x10f0), val);
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if (addr & 0xF) {
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return;
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}
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if (addr == 0x10f0) {
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if (addr == 0) {
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/* TFRR */
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opp->tfrr = val;
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return;
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}
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addr -= 0x10; /* correct for TFRR */
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idx = (addr >> 6) & 0x3;
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addr = addr & 0x30;
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switch (addr & 0x30) {
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case 0x00: /* TCCR */
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@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
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uint32_t retval = -1;
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int idx;
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DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
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DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0);
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if (addr & 0xF) {
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goto out;
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}
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idx = (addr >> 6) & 0x3;
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if (addr == 0x0) {
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if (addr == 0) {
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/* TFRR */
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retval = opp->tfrr;
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goto out;
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}
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addr -= 0x10; /* correct for TFRR */
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idx = (addr >> 6) & 0x3;
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switch (addr & 0x30) {
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case 0x00: /* TCCR */
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retval = opp->timers[idx].tccr;
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@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
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case 0x10: /* TBCR */
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retval = opp->timers[idx].tbcr;
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break;
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case 0x20: /* TIPV */
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case 0x20: /* TVPR */
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retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
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break;
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case 0x30: /* TIDE (TIDR) */
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case 0x30: /* TDR */
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retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
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break;
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}
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