acpi/gpex: Extract two APIs from acpi_dsdt_add_pci
Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc from acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: Yubo Miao <miaoyubo@huawei.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20201119014841.7298-2-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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4aedda25e8
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@ -2,21 +2,11 @@
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#include "hw/acpi/aml-build.h"
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#include "hw/pci-host/gpex.h"
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void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
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{
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int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
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Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
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Aml *method, *crs;
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int i, slot_no;
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Aml *dev = aml_device("%s", "PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(0)));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
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aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
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/* Declare the PCI Routing Table. */
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Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
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for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
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@ -34,7 +24,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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/* Create GSI link device */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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uint32_t irqs = cfg->irq + i;
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uint32_t irqs = irq + i;
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Aml *dev_gsi = aml_device("GSI%d", i);
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aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
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aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
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@ -52,43 +42,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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aml_append(dev_gsi, method);
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aml_append(dev, dev_gsi);
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}
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}
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method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_int(cfg->ecam.base)));
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aml_append(dev, method);
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Aml *rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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if (cfg->mmio32.size) {
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aml_append(rbuf,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio32.base,
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cfg->mmio32.base + cfg->mmio32.size - 1,
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0x0000,
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cfg->mmio32.size));
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}
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if (cfg->pio.size) {
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, 0x0000,
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cfg->pio.size - 1,
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cfg->pio.base,
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cfg->pio.size));
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}
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if (cfg->mmio64.size) {
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aml_append(rbuf,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio64.base,
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cfg->mmio64.base + cfg->mmio64.size - 1,
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0x0000,
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cfg->mmio64.size));
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}
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aml_append(dev, aml_name_decl("_CRS", rbuf));
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static void acpi_dsdt_add_pci_osc(Aml *dev)
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{
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Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
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/* Declare an _OSC (OS Control Handoff) method */
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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@ -160,6 +118,62 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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buf = aml_buffer(1, byte_list);
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aml_append(method, aml_return(buf));
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aml_append(dev, method);
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}
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void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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{
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int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
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Aml *method, *crs, *dev, *rbuf;
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dev = aml_device("%s", "PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(0)));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
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aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
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acpi_dsdt_add_pci_route_table(dev, cfg->irq);
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method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_int(cfg->ecam.base)));
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aml_append(dev, method);
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rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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if (cfg->mmio32.size) {
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aml_append(rbuf,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio32.base,
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cfg->mmio32.base + cfg->mmio32.size - 1,
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0x0000,
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cfg->mmio32.size));
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}
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if (cfg->pio.size) {
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, 0x0000,
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cfg->pio.size - 1,
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cfg->pio.base,
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cfg->pio.size));
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}
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if (cfg->mmio64.size) {
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aml_append(rbuf,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->mmio64.base,
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cfg->mmio64.base + cfg->mmio64.size - 1,
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0x0000,
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cfg->mmio64.size));
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}
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aml_append(dev, aml_name_decl("_CRS", rbuf));
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acpi_dsdt_add_pci_osc(dev);
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Aml *dev_res0 = aml_device("%s", "RES0");
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aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
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