From a10c64e0df3acbefdee1b2b837f76f05b0231aae Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 14 May 2014 17:14:51 -0400 Subject: [PATCH] tcg-s390: Implement direct chaining of TBs Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 9 +++++++++ tcg/s390/tcg-target.c | 4 +++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 444b4d9a1d..8bc2eb663e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -131,6 +131,7 @@ static inline void tlb_flush(CPUState *cpu, int flush_global) #if defined(__arm__) || defined(_ARCH_PPC) \ || defined(__x86_64__) || defined(__i386__) \ || defined(__sparc__) || defined(__aarch64__) \ + || defined(__s390x__) \ || defined(CONFIG_TCG_INTERPRETER) #define USE_DIRECT_JUMP #endif @@ -232,6 +233,14 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4)); /* no need to flush icache explicitly */ } +#elif defined(__s390x__) +static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +{ + /* patch the branch destination */ + intptr_t disp = addr - (jmp_addr - 2); + stl_be_p((void*)jmp_addr, disp / 2); + /* no need to flush icache explicitly */ +} #elif defined(__aarch64__) void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); #define tb_set_jmp_target1 aarch64_tb_set_jmp_target diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index e235130a43..07164e544d 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -1703,7 +1703,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: if (s->tb_jmp_offset) { - tcg_abort(); + tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); + s->tb_jmp_offset[args[0]] = tcg_current_code_size(s); + s->code_ptr += 2; } else { /* load address stored at s->tb_next + args[0] */ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, s->tb_next + args[0]);