target/arm: Implement VFP fp16 VCVT between float and fixed-point
Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-16-peter.maydell@linaro.org
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@ -2972,6 +2972,65 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
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return true;
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}
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static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
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{
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TCGv_i32 vd, shift;
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TCGv_ptr fpst;
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int frac_bits;
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if (!dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
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vd = tcg_temp_new_i32();
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neon_load_reg32(vd, a->vd);
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fpst = fpstatus_ptr(FPST_FPCR_F16);
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shift = tcg_const_i32(frac_bits);
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/* Switch on op:U:sx bits */
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switch (a->opc) {
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case 0:
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gen_helper_vfp_shtoh(vd, vd, shift, fpst);
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break;
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case 1:
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gen_helper_vfp_sltoh(vd, vd, shift, fpst);
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break;
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case 2:
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gen_helper_vfp_uhtoh(vd, vd, shift, fpst);
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break;
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case 3:
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gen_helper_vfp_ultoh(vd, vd, shift, fpst);
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break;
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case 4:
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gen_helper_vfp_toshh_round_to_zero(vd, vd, shift, fpst);
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break;
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case 5:
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gen_helper_vfp_toslh_round_to_zero(vd, vd, shift, fpst);
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break;
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case 6:
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gen_helper_vfp_touhh_round_to_zero(vd, vd, shift, fpst);
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break;
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case 7:
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gen_helper_vfp_toulh_round_to_zero(vd, vd, shift, fpst);
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break;
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default:
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g_assert_not_reached();
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}
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neon_store_reg32(vd, a->vd);
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tcg_temp_free_i32(vd);
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tcg_temp_free_i32(shift);
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tcg_temp_free_ptr(fpst);
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return true;
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}
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static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
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{
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TCGv_i32 vd, shift;
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@ -225,6 +225,8 @@ VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
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# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
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# for the convenience of the trans_VCVT_fix functions.
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%vcvt_fix_op 18:1 16:1 7:1
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VCVT_fix_hp ---- 1110 1.11 1.1. .... 1001 .1.0 .... \
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vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
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VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
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vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
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VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
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